Saved in:
| Main Authors: | , , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2601.19900 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866910002947555328 |
|---|---|
| author | Oswald, William Renteria-Pinon, Mario Hossain, Md. Sajjad Mooney, Kyle Hossain, Md. Bipul Diggs, Destinie Xu, Yiwen Shaban, Mohamed Wang, Jinhui Gong, Na |
| author_facet | Oswald, William Renteria-Pinon, Mario Hossain, Md. Sajjad Mooney, Kyle Hossain, Md. Bipul Diggs, Destinie Xu, Yiwen Shaban, Mohamed Wang, Jinhui Gong, Na |
| contents | Bit truncation has demonstrated great potential to enable run-time quality-power adaptive data storage, thereby optimizing the power/energy efficiency of approximate applications and supporting their deployment in edge environments. However, existing bit-truncation memories require custom designs for a specific application. In this paper, we present a novel bit-truncation memory with full adaptation flexibility, which can truncate any number of data bits at run time to meet different quality and power trade-off requirements for various approximate applications. The developed bit-truncation memory has been applied to two representative data-intensive approximate applications: video processing and deep learning. Our experiments show that the proposed memory can support three different video applications (including luminance-aware, content-aware, and region-of-interest-aware) with enhanced power efficiency (up to 47.02% power savings) as compared to state-of-the-art. In addition, the proposed memory achieves significant (up to 51.69%) power savings for both baseline and pruned lightweight deep learning models, respectively, with a low implementation cost (2.89% silicon area overhead). |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_19900 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Flexible Bit-Truncation Memory for Approximate Applications on the Edge Oswald, William Renteria-Pinon, Mario Hossain, Md. Sajjad Mooney, Kyle Hossain, Md. Bipul Diggs, Destinie Xu, Yiwen Shaban, Mohamed Wang, Jinhui Gong, Na Hardware Architecture Bit truncation has demonstrated great potential to enable run-time quality-power adaptive data storage, thereby optimizing the power/energy efficiency of approximate applications and supporting their deployment in edge environments. However, existing bit-truncation memories require custom designs for a specific application. In this paper, we present a novel bit-truncation memory with full adaptation flexibility, which can truncate any number of data bits at run time to meet different quality and power trade-off requirements for various approximate applications. The developed bit-truncation memory has been applied to two representative data-intensive approximate applications: video processing and deep learning. Our experiments show that the proposed memory can support three different video applications (including luminance-aware, content-aware, and region-of-interest-aware) with enhanced power efficiency (up to 47.02% power savings) as compared to state-of-the-art. In addition, the proposed memory achieves significant (up to 51.69%) power savings for both baseline and pruned lightweight deep learning models, respectively, with a low implementation cost (2.89% silicon area overhead). |
| title | Flexible Bit-Truncation Memory for Approximate Applications on the Edge |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2601.19900 |