ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
Fuente:
arXiv
Saved in:
| Main Authors: | Yu, Zhongkai, Zhou, Chenyang, Lin, Yichen, Zhang, Hejia, Ye, Haotian, Cui, Junxia, Pan, Zaifeng, Zhao, Jishen, Ding, Yufei |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
by: Yu, Zhongkai, et al.
Published: (2026)
by: Yu, Zhongkai, et al.
Published: (2026)
SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)
ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
by: Bai, Kangbo, et al.
Published: (2026)
by: Bai, Kangbo, et al.
Published: (2026)
FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design
by: Nazzal, Mahmoud, et al.
Published: (2025)
by: Nazzal, Mahmoud, et al.
Published: (2025)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)
by: Krupp, Lukas, et al.
Published: (2026)
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
by: Nakkab, Andre, et al.
Published: (2024)
by: Nakkab, Andre, et al.
Published: (2024)
HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
by: Tsai, Pei-Huan, et al.
Published: (2026)
by: Tsai, Pei-Huan, et al.
Published: (2026)
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
by: Wan, Gwok-Waa, et al.
Published: (2025)
by: Wan, Gwok-Waa, et al.
Published: (2025)
LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems
by: Ye, Bochen, et al.
Published: (2025)
by: Ye, Bochen, et al.
Published: (2025)
Large Processor Chip Model
by: Chang, Kaiyan, et al.
Published: (2025)
by: Chang, Kaiyan, et al.
Published: (2025)
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
by: Zhu, Jingchen, et al.
Published: (2024)
by: Zhu, Jingchen, et al.
Published: (2024)
Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
by: Wang, Zhihai, et al.
Published: (2024)
by: Wang, Zhihai, et al.
Published: (2024)
Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization
by: ouyang, Yikang, et al.
Published: (2026)
by: ouyang, Yikang, et al.
Published: (2026)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
MAGE: A Multi-Agent Engine for Automated RTL Code Generation
by: Zhao, Yujie, et al.
Published: (2024)
by: Zhao, Yujie, et al.
Published: (2024)
Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips
by: Chen, Peilin, et al.
Published: (2025)
by: Chen, Peilin, et al.
Published: (2025)
HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV
by: Shijie, Liu, et al.
Published: (2026)
by: Shijie, Liu, et al.
Published: (2026)
Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
by: Ainsworth, Sam, et al.
Published: (2024)
by: Ainsworth, Sam, et al.
Published: (2024)
3D MPSoC with On-Chip Cache Support -- Design and Exploitation
by: Cataldo, Rodrigo, et al.
Published: (2025)
by: Cataldo, Rodrigo, et al.
Published: (2025)
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
by: Fang, Wenji, et al.
Published: (2025)
by: Fang, Wenji, et al.
Published: (2025)
Improving Chip Design Enablement for Universities in Europe -- A Position Paper
by: Krupp, Lukas, et al.
Published: (2025)
by: Krupp, Lukas, et al.
Published: (2025)
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
by: Deng, Chenhui, et al.
Published: (2024)
by: Deng, Chenhui, et al.
Published: (2024)
WIP: Turning Fake Chips into Learning Opportunities
by: Mehraban, Haniye, et al.
Published: (2025)
by: Mehraban, Haniye, et al.
Published: (2025)
HWE-Bench: Can Language Models Perform Board-level Schematic Designs?
by: Qiu, Weibo, et al.
Published: (2026)
by: Qiu, Weibo, et al.
Published: (2026)
Resilient and Secure Programmable System-on-Chip Accelerator Offload
by: Gouveia, Inês Pinto, et al.
Published: (2024)
by: Gouveia, Inês Pinto, et al.
Published: (2024)
A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)
by: Kim, Jeongeun, et al.
Published: (2025)
QiMeng: Fully Automated Hardware and Software Design for Processor Chip
by: Zhang, Rui, et al.
Published: (2025)
by: Zhang, Rui, et al.
Published: (2025)
HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
by: Tang, Jinwei, et al.
Published: (2024)
by: Tang, Jinwei, et al.
Published: (2024)
Algorithm-Driven On-Chip Integration for High Density and Low Cost
by: Kim, Jeongeun, et al.
Published: (2025)
by: Kim, Jeongeun, et al.
Published: (2025)
EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations
by: Choi, Sangun, et al.
Published: (2025)
by: Choi, Sangun, et al.
Published: (2025)
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
by: Zuckerman, Joseph, et al.
Published: (2024)
by: Zuckerman, Joseph, et al.
Published: (2024)
Rainbow: A Composable Coherence Protocol for Multi-Chip Servers
by: Menezo, Lucia G., et al.
Published: (2020)
by: Menezo, Lucia G., et al.
Published: (2020)
BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
by: Xue, Ke, et al.
Published: (2025)
by: Xue, Ke, et al.
Published: (2025)
Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip
by: Zaeemi, Meysam, et al.
Published: (2026)
by: Zaeemi, Meysam, et al.
Published: (2026)
A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
by: Zhou, Wenyong, et al.
Published: (2025)
by: Zhou, Wenyong, et al.
Published: (2025)
Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs
by: Bochem, Severin, et al.
Published: (2024)
by: Bochem, Severin, et al.
Published: (2024)
Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design
by: Ai, Chenyang, et al.
Published: (2026)
by: Ai, Chenyang, et al.
Published: (2026)
ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools
by: Wanna, Andy, et al.
Published: (2025)
by: Wanna, Andy, et al.
Published: (2025)
AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving
by: Yu, Zhongkai, et al.
Published: (2026)
by: Yu, Zhongkai, et al.
Published: (2026)
Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
by: Huang, Zongle, et al.
Published: (2026)
by: Huang, Zongle, et al.
Published: (2026)
Similar Items
-
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
by: Yu, Zhongkai, et al.
Published: (2026) -
SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025) -
ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
by: Bai, Kangbo, et al.
Published: (2026) -
FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design
by: Nazzal, Mahmoud, et al.
Published: (2025) -
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)