Weight-four parity checks with silicon spin qubits

Fuente: arXiv
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Main Authors: Undseth, Brennan, Meggiato, Nicola, Wu, Yi-Hsien, Katiraee-Far, Sam R., Tryputen, Larysa, de Snoo, Sander L., Esposti, Davide Degli, Scappucci, Giordano, Greplová, Eliška, Vandersypen, Lieven M. K.
Format: Preprint
Published: 2026
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author Undseth, Brennan
Meggiato, Nicola
Wu, Yi-Hsien
Katiraee-Far, Sam R.
Tryputen, Larysa
de Snoo, Sander L.
Esposti, Davide Degli
Scappucci, Giordano
Greplová, Eliška
Vandersypen, Lieven M. K.
author_facet Undseth, Brennan
Meggiato, Nicola
Wu, Yi-Hsien
Katiraee-Far, Sam R.
Tryputen, Larysa
de Snoo, Sander L.
Esposti, Davide Degli
Scappucci, Giordano
Greplová, Eliška
Vandersypen, Lieven M. K.
contents Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.
format Preprint
id arxiv_https___arxiv_org_abs_2601_23267
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle Weight-four parity checks with silicon spin qubits
Undseth, Brennan
Meggiato, Nicola
Wu, Yi-Hsien
Katiraee-Far, Sam R.
Tryputen, Larysa
de Snoo, Sander L.
Esposti, Davide Degli
Scappucci, Giordano
Greplová, Eliška
Vandersypen, Lieven M. K.
Mesoscale and Nanoscale Physics
Quantum Physics
Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.
title Weight-four parity checks with silicon spin qubits
topic Mesoscale and Nanoscale Physics
Quantum Physics
url https://arxiv.org/abs/2601.23267