Cover Image

ENFOR-SA: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate DNN Reliability Assessment on Systolic Arrays

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Tonetto, Rafael Billig, Traiola, Marcello, Santos, Fernando Fernandes dos, Kritikakou, Angeliki
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction
by: Traiola, Marcello, et al.
Published: (2025)

KAN-SAs: Efficient Acceleration of Kolmogorov-Arnold Networks on Systolic Arrays
by: Errabii, Sohaib, et al.
Published: (2025)

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference
by: Cherezova, Natalia, et al.
Published: (2025)

AxMoE: Characterizing the Impact of Approximate Multipliers on Mixture-of-Experts DNN Architectures
by: Shende, Omkar B, et al.
Published: (2026)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

KANtize: Exploring Low-bit Quantization of Kolmogorov-Arnold Networks for Efficient Inference
by: Errabii, Sohaib, et al.
Published: (2026)

Error Checking for Sparse Systolic Tensor Arrays
by: Peltekis, Christodoulos, et al.
Published: (2024)

ONE-SA: Enabling Nonlinear Operations in Systolic Arrays for Efficient and Flexible Neural Network Inference
by: Sun, Ruiqi, et al.
Published: (2024)

SA-Kura: An Energy-Efficient Systolic Array Accelerator for Locally-Coupled Kuramoto Drift in Diffusion Sampling
by: Jin, Jeongmin, et al.
Published: (2026)

Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays
by: Siddique, Ayesha, et al.
Published: (2025)

ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Acceleration
by: Abdelmaksoud, Ahmed J., et al.
Published: (2025)

PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators
by: Sun, Xiaotian, et al.
Published: (2024)

SystolicAttention: Fusing FlashAttention within a Single Systolic Array
by: Lin, Jiawei, et al.
Published: (2025)

Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks
by: Raja, Tejas
Published: (2024)

Domain-specific Hardware Acceleration for Model Predictive Path Integral Control
by: Tanguy-Legac, Erwan, et al.
Published: (2026)

Voyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators
by: Prabhu, Kartik, et al.
Published: (2025)

A Micro Architectural Events Aware Real-Time Embedded System Fault Injector
by: Magliano, Enrico, et al.
Published: (2024)

Systolic Array Acceleration of Diagonal-Optimized Sparse-Sparse Matrix Multiplication for Efficient Quantum Simulation
by: Su, Yuchao, et al.
Published: (2025)

Periodic Online Testing for Sparse Systolic Tensor Arrays
by: Peltekis, Christodoulos, et al.
Published: (2025)

ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array
by: Han, Meng, et al.
Published: (2023)

PowerFlow-DNN: Compiler-Directed Fine-Grained Power Orchestration for End-to-End Edge AI Inference
by: Chen, Paul, et al.
Published: (2026)

Efficient yet Accurate End-to-End SC Accelerator Design
by: Li, Meng, et al.
Published: (2024)

Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster
by: Cai, Maoyuan, et al.
Published: (2026)

FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors
by: Venkatasubramanian, Logashree, et al.
Published: (2026)

Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference
by: Chen, Chun-Ting, et al.
Published: (2025)

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques
by: Canpolat, Oğuzhan, et al.
Published: (2025)

Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
by: Liu, Yuhao, et al.
Published: (2026)

Single-Event Upset Analysis of a Systolic Array based Deep Neural Network Accelerator
by: Jonckers, Naïn, et al.
Published: (2024)

Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
by: Rogenmoser, Michael, et al.
Published: (2026)

WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on the Versal ACAP Architecture
by: Dai, Tuo, et al.
Published: (2024)

DRIFT: Harnessing Inherent Fault Tolerance for Efficient and Reliable Diffusion Model Inference
by: Wen, Jinqi, et al.
Published: (2026)

TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling
by: Sestito, Cristian, et al.
Published: (2024)

DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization
by: Ren, Yi, et al.
Published: (2025)

Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
by: Li, Jindong, et al.
Published: (2024)

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration
by: Taka, Endri, et al.
Published: (2025)

A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator
by: Huang, Sixiao, et al.
Published: (2025)

Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters
by: Mazzola, Sergio, et al.
Published: (2024)

ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
by: Xie, Tong, et al.
Published: (2025)

Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
by: Malhotra, Akul, et al.
Published: (2025)