Cover Image

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Pham, Anh Kiet, Vo, Van Truong, Le, Vu Trung Duong, Vu, Tuan Hai, Pham, Hoai Luan, Nguyen, Van Tinh, Nakashima, Yasuhiko
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Cryptography and Security
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
by: Nguyen, Van Tinh, et al.
Published: (2025)

FQsun: A Configurable Wave Function-Based Quantum Emulator for Power-Efficient Quantum Simulations
by: Vu, Tuan Hai, et al.
Published: (2024)

Theoretical Analysis of the Efficient-Memory Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs
by: Le, Tran Xuan Hieu, et al.
Published: (2024)

Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation
by: Tran, Van Duy, et al.
Published: (2024)

A Protocol-Aware P4 Pipeline for MQTT Security and Anomaly Mitigation in Edge IoT Systems
by: Binh, Bui Ngoc Thanh, et al.
Published: (2026)

Parallelizing the stabilizer formalism for quantum machine learning applications
by: Hai, Vu Tuan, et al.
Published: (2025)

PACOX: A FPGA-based Pauli Composer Accelerator for Pauli String Computation
by: Le, Tran Xuan Hieu, et al.
Published: (2026)

QEA: An Accelerator for Quantum Circuit Simulation with Resources Efficiency and Flexibility
by: Tran, Van Duy, et al.
Published: (2025)

HPQEA: A Scalable and High-Performance Quantum Emulator with High-Bandwidth Memory for Diverse Algorithms Support
by: Van Duy, Tran, et al.
Published: (2025)

Transfer-Based Strategies for Multi-Target Quantum Optimization
by: Hai, Vu Tuan, et al.
Published: (2025)

Qimax: Efficient quantum simulation via GPU-accelerated extended stabilizer formalism
by: Hai, Vu Tuan, et al.
Published: (2025)

ZeroSlide: Is Zero-Shot Classification Adequate for Lifelong Learning in Whole-Slide Image Analysis in the Era of Pathology Vision-Language Foundation Models?
by: Bui, Doanh C., et al.
Published: (2025)

Lifelong Whole Slide Image Analysis: Online Vision-Language Adaptation and Past-to-Present Gradient Distillation
by: Bui, Doanh C., et al.
Published: (2025)

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
by: Darvishi, Mostafa
Published: (2025)

Implementation and Optimization of HQC Decoding on NPU-Integrated Devices
by: Chau, Vu Minh, et al.
Published: (2026)

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges
by: Zhong, Xinchao, et al.
Published: (2024)

Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)

Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications
by: Sharma, Vijay Pratap, et al.
Published: (2026)

Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)

Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)

Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)

Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator
by: Ando, Takuto, et al.
Published: (2025)

SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security
by: Ewert, Christian, et al.
Published: (2026)

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
by: Harlikar, Pracheta, et al.
Published: (2025)

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
by: Rezunov, Evgenii, et al.
Published: (2025)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
by: Ottaviano, Alessandro, et al.
Published: (2023)

Flexing RISC-V Instruction Subset Processors to Extreme Edge
by: Raisiardali, Alireza, et al.
Published: (2025)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
by: Colagrande, Luca, et al.
Published: (2025)

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
by: McDougall, Ian, et al.
Published: (2025)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025)

A High Performance and Efficient Post-Quantum Crypto-Processor for FrodoKEM
by: Li, Kai, et al.
Published: (2026)

Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA
by: Ando, Takuto, et al.
Published: (2025)

Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA
by: Ando, Takuto, et al.
Published: (2025)

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
by: Wang, Chuanning, et al.
Published: (2024)

Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
by: Wang, Weiying, et al.
Published: (2026)

An FPGA Compiler for On-the-Fly Adaptive CNN Deployment and Reconfiguration
by: Mazouz, Alaa, et al.
Published: (2025)