Evolutionary Mapping of Neural Networks to Spatial Accelerators
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arXiv
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| Format: | Preprint |
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2026
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| author | Pierro, Alessandro Timcheck, Jonathan Yik, Jason Lindauer, Marius Hüllermeier, Eyke Wever, Marcel |
| author_facet | Pierro, Alessandro Timcheck, Jonathan Yik, Jason Lindauer, Marius Hüllermeier, Eyke Wever, Marcel |
| contents | Spatial accelerators, composed of arrays of compute-memory integrated units, offer an attractive platform for deploying inference workloads with low latency and low energy consumption. However, fully exploiting their architectural advantages typically requires careful, expert-driven mapping of computational graphs to distributed processing elements. In this work, we automate this process by framing the mapping challenge as a black-box optimization problem. We introduce the first evolutionary, hardware-in-the-loop mapping framework for neuromorphic accelerators, enabling users without deep hardware knowledge to deploy workloads more efficiently. We evaluate our approach on Intel Loihi 2, a representative spatial accelerator featuring 152 cores per chip in a 2D mesh. Our method achieves up to 35% reduction in total latency compared to default heuristics on two sparse multi-layer perceptron networks. Furthermore, we demonstrate the scalability of our approach to multi-chip systems and observe an up to 40% improvement in energy efficiency, without explicitly optimizing for it. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_04717 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Evolutionary Mapping of Neural Networks to Spatial Accelerators Pierro, Alessandro Timcheck, Jonathan Yik, Jason Lindauer, Marius Hüllermeier, Eyke Wever, Marcel Neural and Evolutionary Computing Spatial accelerators, composed of arrays of compute-memory integrated units, offer an attractive platform for deploying inference workloads with low latency and low energy consumption. However, fully exploiting their architectural advantages typically requires careful, expert-driven mapping of computational graphs to distributed processing elements. In this work, we automate this process by framing the mapping challenge as a black-box optimization problem. We introduce the first evolutionary, hardware-in-the-loop mapping framework for neuromorphic accelerators, enabling users without deep hardware knowledge to deploy workloads more efficiently. We evaluate our approach on Intel Loihi 2, a representative spatial accelerator featuring 152 cores per chip in a 2D mesh. Our method achieves up to 35% reduction in total latency compared to default heuristics on two sparse multi-layer perceptron networks. Furthermore, we demonstrate the scalability of our approach to multi-chip systems and observe an up to 40% improvement in energy efficiency, without explicitly optimizing for it. |
| title | Evolutionary Mapping of Neural Networks to Spatial Accelerators |
| topic | Neural and Evolutionary Computing |
| url | https://arxiv.org/abs/2602.04717 |