System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
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2026
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| author | Cunha, Luis Martins, Jose Rodriguez, Manuel Gomes, Tiago Pinto, Sandro Moslehner, Uwe Dieffenbach, Kai Farrall, Glenn Nuernberger, Kajetan Roecker, Thomas |
| author_facet | Cunha, Luis Martins, Jose Rodriguez, Manuel Gomes, Tiago Pinto, Sandro Moslehner, Uwe Dieffenbach, Kai Farrall, Glenn Nuernberger, Kajetan Roecker, Thomas |
| contents | As RISC-V adoption accelerates, domains such as automotive, the Internet of Things (IoT), and industrial control are attracting growing attention. These domains are subject to stringent Size, Weight, Power, and Cost (SWaP-C) constraints, which have driven a shift toward heterogeneous Systems-on-Chip (SoCs) integrating general-purpose CPUs, tightly coupled accelerators, and diverse I/O devices with different integrity levels. While such integration improves cost efficiency and performance, it introduces a fundamental safety and security challenge: enforcing system-level isolation in mixed-criticality environments. Although RISC-V International has proposed several hardware isolation primitives, including RISC-V Worlds, IOPMP, and SmMTT, their interoperability, scalability, and suitability for real-time systems remain insufficiently understood. In this paper, we present a comparative analysis of these primitives from the perspective of practical heterogeneous SoC designs. We implement an IOPMP, a World-based checker, and a modified RISC-V World checker that addresses key limitations of the baseline specification, and evaluate their trade-offs in terms of security guarantees and power-performance-area (PPA). Our results show that the World-based checker introduces a fixed, configuration-independent access latency, achieving lower worst-case delay than the evaluated alternatives while scaling predictably with system size. At the macro level, we estimate that the proposed modifications reduce SoC area by up to approximately 5% compared to a baseline design. All artifacts will be released as open source, and we expect these findings to directly contribute to the evolution and ratification of RISC-V specifications, as well as to the design of future RISC-V SoCs. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2602_05002 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check Cunha, Luis Martins, Jose Rodriguez, Manuel Gomes, Tiago Pinto, Sandro Moslehner, Uwe Dieffenbach, Kai Farrall, Glenn Nuernberger, Kajetan Roecker, Thomas Cryptography and Security Hardware Architecture As RISC-V adoption accelerates, domains such as automotive, the Internet of Things (IoT), and industrial control are attracting growing attention. These domains are subject to stringent Size, Weight, Power, and Cost (SWaP-C) constraints, which have driven a shift toward heterogeneous Systems-on-Chip (SoCs) integrating general-purpose CPUs, tightly coupled accelerators, and diverse I/O devices with different integrity levels. While such integration improves cost efficiency and performance, it introduces a fundamental safety and security challenge: enforcing system-level isolation in mixed-criticality environments. Although RISC-V International has proposed several hardware isolation primitives, including RISC-V Worlds, IOPMP, and SmMTT, their interoperability, scalability, and suitability for real-time systems remain insufficiently understood. In this paper, we present a comparative analysis of these primitives from the perspective of practical heterogeneous SoC designs. We implement an IOPMP, a World-based checker, and a modified RISC-V World checker that addresses key limitations of the baseline specification, and evaluate their trade-offs in terms of security guarantees and power-performance-area (PPA). Our results show that the World-based checker introduces a fixed, configuration-independent access latency, achieving lower worst-case delay than the evaluated alternatives while scaling predictably with system size. At the macro level, we estimate that the proposed modifications reduce SoC area by up to approximately 5% compared to a baseline design. All artifacts will be released as open source, and we expect these findings to directly contribute to the evolution and ratification of RISC-V specifications, as well as to the design of future RISC-V SoCs. |
| title | System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2602.05002 |