Cover Image

Codes for Metastability-Containing Addition

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Bund, Johannes, Lenzen, Christoph, Medina, Moti
Format:	Preprint
Published:	2026
Subjects:	Information Theory Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Unrolled and Pipelined Decoders based on Look-Up Tables for Polar Codes
by: Giard, Pascal, et al.
Published: (2023)

Towards High-Performance Network Coding: FPGA Acceleration With Bounded-value Generators
by: Qing, Jiaxin, et al.
Published: (2025)

Unraveling codes: fast, robust, beyond-bound error correction for DRAM
by: Hamburg, Mike, et al.
Published: (2024)

Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory
by: Shi, Daijing, et al.
Published: (2025)

Hardware Implementation of Projection-Aggregation Decoders for Reed-Muller Codes
by: Hashemipour-Nazari, Marzieh, et al.
Published: (2024)

Beamspace Equalization for mmWave Massive MIMO: Algorithms and VLSI Implementations
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2025)

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation
by: Ren, Yuqing, et al.
Published: (2023)

Latch Based Design for Fast Voltage Droop Response
by: Srinivas, Shreyas, et al.
Published: (2025)

FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors
by: Venkatasubramanian, Logashree, et al.
Published: (2026)

The maximum storage capacity of open-loop written RRAM is around 4 bits
by: Li, Yongxiang, et al.
Published: (2024)

Ray Antenna Array: A Novel Cost-Effective Multi-Antenna Architecture for Enhanced Wireless Communication
by: Dong, Zhenjun, et al.
Published: (2025)

SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation
by: Lyu, Shengzhe, et al.
Published: (2026)

Reconfigurable Intelligent Surfaces for THz: Hardware Design and Signal Processing Challenges
by: Alexandropoulos, George C., et al.
Published: (2024)

Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications
by: Krishna, L. Hemanth, et al.
Published: (2025)

Metastability-Containing Turing Machines
by: Bund, Johannes, et al.
Published: (2026)

RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS): A Structured Methodology Using Large Language Models for Hardware Design
by: Ahir, Shiva, et al.
Published: (2026)

Online Alignment and Addition in Multi-Term Floating-Point Adders
by: Alexandridis, Kosmas, et al.
Published: (2024)

Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-scalar Multiplication
by: Ohno, Ayumi, et al.
Published: (2025)

Small Hazard-free Transducers
by: Bund, Johannes, et al.
Published: (2018)

GEN-Graph: Heterogeneous PIM Accelerator for General Computational Patterns in Graph-based Dynamic Programming
by: Chen, Yanru, et al.
Published: (2026)

The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates
by: Ilmberger, Joscha, et al.
Published: (2025)

Code size reduction by advanced near addressing modes
by: Nuernberger, Kajetan, et al.
Published: (2026)

Error Detection and Correction Codes for Safe In-Memory Computations
by: Parrini, Luca, et al.
Published: (2024)

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)

LLM-Powered Code Analysis and Optimization for Gaussian Splatting Kernels
by: Hu, Yi, et al.
Published: (2025)

LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs
by: Sun, Miao, et al.
Published: (2026)

Attacking AI Accelerators by Leveraging Arithmetic Properties of Addition
by: Heidary, Masoud, et al.
Published: (2026)

High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms
by: Wang, Hao, et al.
Published: (2024)

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
by: Xie, Rui, et al.
Published: (2025)

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)

Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs
by: Lowe, Sean, et al.
Published: (2026)

A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2024)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)

Sustainable operation of research infrastructure for novel computing
by: Stradmann, Yannik, et al.
Published: (2025)

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
by: Lei, Jie, et al.
Published: (2026)

SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models
by: Xia, Yuhuan, et al.
Published: (2026)

Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
by: Ma, Ruiyang, et al.
Published: (2025)

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
by: Tan, Yan, et al.
Published: (2025)

HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation
by: Abdollahi, Armin, et al.
Published: (2026)

FaTRQ: Tiered Residual Quantization for LLM Vector Search in Far-Memory-Aware ANNS Systems
by: Zhang, Tianqi, et al.
Published: (2026)