:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Author:	Benz, Thomas
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2602.09554
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
by: Benz, Thomas, et al.
Published: (2025)

A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems
by: Liang, Chaoqun, et al.
Published: (2024)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
by: Rogenmoser, Michael, et al.
Published: (2024)

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
by: Benz, Thomas, et al.
Published: (2025)

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
by: Ottaviano, Alessandro, et al.
Published: (2024)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
by: Garofalo, Angelo, et al.
Published: (2025)

Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring
by: Liang, Chaoqun, et al.
Published: (2025)

HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
by: Sauter, Philippe, et al.
Published: (2026)

Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
by: Jiang, He, et al.
Published: (2025)

Realizing Hardware-Optimized General Tree-Based Data Structures for Heterogeneous System Classes
by: Biebert, Daniel, et al.
Published: (2025)

Real-Time, Energy-Efficient, Sampling-Based Optimal Control via FPGA Acceleration
by: Desai, Tanmay, et al.
Published: (2026)

Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking
by: Mazzola, Sergio, et al.
Published: (2025)

PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance
by: Ji, Shixin, et al.
Published: (2026)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
by: Fischer, Tim, et al.
Published: (2024)

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
by: Sauter, Philippe, et al.
Published: (2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)

FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators
by: Zhang, Chi, et al.
Published: (2025)

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
by: Scheffler, Paul, et al.
Published: (2025)

Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous Representations
by: Hu, Zhang, et al.
Published: (2025)

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
by: Sauter, Philippe, et al.
Published: (2025)

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
by: Colagrande, Luca, et al.
Published: (2025)

Energy-adaptive Buffering for Efficient, Responsive, and Persistent Batteryless Systems
by: Williams, Harrison, et al.
Published: (2024)

High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator
by: Lin, Kuan-Ting, et al.
Published: (2025)

A Survey of Real-time Scheduling on Accelerator-based Heterogeneous Architecture for Time Critical Applications
by: Zou, An, et al.
Published: (2025)

A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
by: Zhou, Wenyong, et al.
Published: (2025)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
by: Vanoni, Axel, et al.
Published: (2026)

Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
by: Sullivan, Connor Rudy, et al.
Published: (2026)

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
by: Sauter, Phillippe, et al.
Published: (2024)

System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
by: Cunha, Luis, et al.
Published: (2026)

Towards an End-To-End System for Real-Time Gesture Recognition from Surface Vibrations
by: Hettstedt, Florian, et al.
Published: (2026)

Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems
by: Sullivan, Connor, et al.
Published: (2024)

Energy-Aware Heterogeneous Federated Learning via Approximate DNN Accelerators
by: Pfeiffer, Kilian, et al.
Published: (2024)

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
by: Jung, Victor J. B., et al.
Published: (2025)

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers
by: Scherer, Moritz, et al.
Published: (2024)

Timing-Driven Global Placement by Efficient Critical Path Extraction
by: Shi, Yunqi, et al.
Published: (2025)

To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems
by: Chen, Xingzhen, et al.
Published: (2026)

A High-Efficiency SoC for Next-Generation Mobile DNA Sequencing
by: Beyene, Abel, et al.
Published: (2025)

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
by: Riedel, Samuel, et al.
Published: (2025)

Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements
by: Shi, Xinyu, et al.
Published: (2024)

Jack Unit: An Area- and Energy-Efficient Multiply-Accumulate (MAC) Unit Supporting Diverse Data Formats
by: Noh, Seock-Hwan, et al.
Published: (2025)