Scaling Routers with In-Package Optics and High-Bandwidth Memories
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866915791017869312 |
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| author | Keslassy, Isaac Yavlovich, Ilay Yallouz, Jose Hsueh, Tzu-Chien Fainman, Yeshaiahu Lin, Bill |
| author_facet | Keslassy, Isaac Yavlovich, Ilay Yallouz, Jose Hsueh, Tzu-Chien Fainman, Yeshaiahu Lin, Bill |
| contents | This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optics. We propose a novel internet router architecture that employs these technologies to achieve a petabit/sec router within a single integrated package. At the top-level, we introduce a novel split-parallel switch architecture that spatially divides (without processing) the incoming fibers and distributes them across smaller independent switches without intermediate OEO conversions or fine-tuned per-packet load-balancing. This passive spatial division enables scaling at the cost of a coarser traffic load balancing. Yet, through extensive evaluations of backbone network traffic, we demonstrate that differences with fine-tuned approaches are small. In addition, we propose a novel HBM-based shared-memory architecture for the implementation of the smaller independent switches, and we introduce a novel parallel frame interleaving algorithm that packs traffic into frames so that HBM banks are accessed at peak HBM data rates in a cyclical interleaving manner. We further discuss why these new technologies represent a paradigm shift in the design of future internet routers. Finally, we emphasize that power consumption may constitute the primary bottleneck to scaling. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_10505 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Scaling Routers with In-Package Optics and High-Bandwidth Memories Keslassy, Isaac Yavlovich, Ilay Yallouz, Jose Hsueh, Tzu-Chien Fainman, Yeshaiahu Lin, Bill Networking and Internet Architecture Hardware Architecture This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optics. We propose a novel internet router architecture that employs these technologies to achieve a petabit/sec router within a single integrated package. At the top-level, we introduce a novel split-parallel switch architecture that spatially divides (without processing) the incoming fibers and distributes them across smaller independent switches without intermediate OEO conversions or fine-tuned per-packet load-balancing. This passive spatial division enables scaling at the cost of a coarser traffic load balancing. Yet, through extensive evaluations of backbone network traffic, we demonstrate that differences with fine-tuned approaches are small. In addition, we propose a novel HBM-based shared-memory architecture for the implementation of the smaller independent switches, and we introduce a novel parallel frame interleaving algorithm that packs traffic into frames so that HBM banks are accessed at peak HBM data rates in a cyclical interleaving manner. We further discuss why these new technologies represent a paradigm shift in the design of future internet routers. Finally, we emphasize that power consumption may constitute the primary bottleneck to scaling. |
| title | Scaling Routers with In-Package Optics and High-Bandwidth Memories |
| topic | Networking and Internet Architecture Hardware Architecture |
| url | https://arxiv.org/abs/2602.10505 |