Reed-Muller Error-Correction Code Encoder for SFQ-to-CMOS Interface Circuits
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866915803456077824 |
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| author | Mustafa, Yerzhan Peköz, Berker Köse, Selçuk |
| author_facet | Mustafa, Yerzhan Peköz, Berker Köse, Selçuk |
| contents | Data transmission from superconducting digital electronics such as single flux quantum (SFQ) logic to semiconductor (CMOS) circuits is subject to bit errors due to, e.g., flux trapping, process parameter variations (PPV), and fabrication defects. In this paper, a lightweight hardware-efficient error-correction code encoder is designed and analyzed. Particularly, a Reed-Muller code RM(1,3) encoder is implemented with SFQ digital logic. The proposed RM(1,3) encoder converts a 4-bit message into an 8-bit codeword and can detect and correct up to 3- and 1-bit errors, respectively. This encoder circuit is designed using MIT-LL SFQ5ee process and SuperTools/ColdFlux RSFQ cell library. A simulation framework integrating JoSIM simulator and MATLAB script for automated data collection and analysis, is proposed to study the performance of RM(1,3) encoder. The proposed encoder improves the probability of having no bit errors by 6.7% as compared to an encoder-less design under $\pm20\%$ PPV. With $\pm15\%$ and lower PPV, the proposed encoder could correct all errors with at least 99.1% probability. The impact of fabrication defects such as open circuit faults on the encoder circuit is also studied using the proposed framework. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2602_11140 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Reed-Muller Error-Correction Code Encoder for SFQ-to-CMOS Interface Circuits Mustafa, Yerzhan Peköz, Berker Köse, Selçuk Signal Processing Superconductivity Hardware Architecture 94C10, 81V80, 94A24, 94B05, 68M15 B.6.1; B.7.1; C.3; E.4 Data transmission from superconducting digital electronics such as single flux quantum (SFQ) logic to semiconductor (CMOS) circuits is subject to bit errors due to, e.g., flux trapping, process parameter variations (PPV), and fabrication defects. In this paper, a lightweight hardware-efficient error-correction code encoder is designed and analyzed. Particularly, a Reed-Muller code RM(1,3) encoder is implemented with SFQ digital logic. The proposed RM(1,3) encoder converts a 4-bit message into an 8-bit codeword and can detect and correct up to 3- and 1-bit errors, respectively. This encoder circuit is designed using MIT-LL SFQ5ee process and SuperTools/ColdFlux RSFQ cell library. A simulation framework integrating JoSIM simulator and MATLAB script for automated data collection and analysis, is proposed to study the performance of RM(1,3) encoder. The proposed encoder improves the probability of having no bit errors by 6.7% as compared to an encoder-less design under $\pm20\%$ PPV. With $\pm15\%$ and lower PPV, the proposed encoder could correct all errors with at least 99.1% probability. The impact of fabrication defects such as open circuit faults on the encoder circuit is also studied using the proposed framework. |
| title | Reed-Muller Error-Correction Code Encoder for SFQ-to-CMOS Interface Circuits |
| topic | Signal Processing Superconductivity Hardware Architecture 94C10, 81V80, 94A24, 94B05, 68M15 B.6.1; B.7.1; C.3; E.4 |
| url | https://arxiv.org/abs/2602.11140 |