RAM-Net: Expressive Linear Attention with Selectively Addressable Memory
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arXiv
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| Hauptverfasser: | , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866908829801775104 |
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| author | Xiao, Kaicheng Li, Haotian Dong, Liran Xing, Guoliang |
| author_facet | Xiao, Kaicheng Li, Haotian Dong, Liran Xing, Guoliang |
| contents | While linear attention architectures offer efficient inference, compressing unbounded history into a fixed-size memory inherently limits expressivity and causes information loss. To address this limitation, we introduce Random Access Memory Network (RAM-Net), a novel architecture designed to bridge the gap between the representational capacity of full attention and the memory efficiency of linear models. The core of RAM-Net maps inputs to high-dimensional sparse vectors serving as explicit addresses, allowing the model to selectively access a massive memory state. This design enables exponential state size scaling without additional parameters, which significantly mitigates signal interference and enhances retrieval fidelity. Moreover, the inherent sparsity ensures exceptional computational efficiency, as state updates are confined to minimal entries. Extensive experiments demonstrate that RAM-Net consistently surpasses state-of-the-art baselines in fine-grained long-range retrieval tasks and achieves competitive performance in standard language modeling and zero-shot commonsense reasoning benchmarks, validating its superior capability to capture complex dependencies with significantly reduced computational overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_11958 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | RAM-Net: Expressive Linear Attention with Selectively Addressable Memory Xiao, Kaicheng Li, Haotian Dong, Liran Xing, Guoliang Machine Learning Computation and Language While linear attention architectures offer efficient inference, compressing unbounded history into a fixed-size memory inherently limits expressivity and causes information loss. To address this limitation, we introduce Random Access Memory Network (RAM-Net), a novel architecture designed to bridge the gap between the representational capacity of full attention and the memory efficiency of linear models. The core of RAM-Net maps inputs to high-dimensional sparse vectors serving as explicit addresses, allowing the model to selectively access a massive memory state. This design enables exponential state size scaling without additional parameters, which significantly mitigates signal interference and enhances retrieval fidelity. Moreover, the inherent sparsity ensures exceptional computational efficiency, as state updates are confined to minimal entries. Extensive experiments demonstrate that RAM-Net consistently surpasses state-of-the-art baselines in fine-grained long-range retrieval tasks and achieves competitive performance in standard language modeling and zero-shot commonsense reasoning benchmarks, validating its superior capability to capture complex dependencies with significantly reduced computational overhead. |
| title | RAM-Net: Expressive Linear Attention with Selectively Addressable Memory |
| topic | Machine Learning Computation and Language |
| url | https://arxiv.org/abs/2602.11958 |