Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
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arXiv
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| Format: | Preprint |
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2026
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| author | Kanda, R. Onizawa, N. Leonardon, M. Gripon, V. Hanyu, T. |
| author_facet | Kanda, R. Onizawa, N. Leonardon, M. Gripon, V. Hanyu, T. |
| contents | This study aims to ensure consistency in accuracy throughout the entire design flow in the implementation of edge AI hardware for few-shot learning, by implementing fixed-point data processing in the pre-training and evaluation phases. Specifically, the quantization module, called Brevitas, is applied to implement fixed-point data processing, which allows for arbitrary specification of the bit widths for the integer and fractional parts. Two methods of fixed-point data quantization, quantization-aware training (QAT) and post-training quantization (PTQ), are utilized in Brevitas. With Tensil, which is used in the current design flow, the bit widths of the integer and fractional parts need to be 8 bits each or 16 bits each when implemented in hardware, but performance validation has shown that accuracy comparable to floating-point operations can be maintained even with 6 bits or 5 bits each, indicating potential for further reduction in computational resources. These results clearly contribute to the creation of a versatile design and evaluation environment for edge AI hardware for few-shot learning. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_12295 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning Kanda, R. Onizawa, N. Leonardon, M. Gripon, V. Hanyu, T. Hardware Architecture This study aims to ensure consistency in accuracy throughout the entire design flow in the implementation of edge AI hardware for few-shot learning, by implementing fixed-point data processing in the pre-training and evaluation phases. Specifically, the quantization module, called Brevitas, is applied to implement fixed-point data processing, which allows for arbitrary specification of the bit widths for the integer and fractional parts. Two methods of fixed-point data quantization, quantization-aware training (QAT) and post-training quantization (PTQ), are utilized in Brevitas. With Tensil, which is used in the current design flow, the bit widths of the integer and fractional parts need to be 8 bits each or 16 bits each when implemented in hardware, but performance validation has shown that accuracy comparable to floating-point operations can be maintained even with 6 bits or 5 bits each, indicating potential for further reduction in computational resources. These results clearly contribute to the creation of a versatile design and evaluation environment for edge AI hardware for few-shot learning. |
| title | Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2602.12295 |