Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
Fuente:
arXiv
Guardado en:
| Autores principales: | Kanda, R., Onizawa, N., Leonardon, M., Gripon, V., Hanyu, T. |
|---|---|
| Formato: | Preprint |
| Publicado: |
2026
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| Materias: | |
| Acceso en línea: | |
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