DPUConfig: Optimizing ML Inference in FPGAs Using Reinforcement Learning
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866911446135209984 |
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| author | Patras, Alexandros Lalis, Spyros Antonopoulos, Christos D. Bellas, Nikolaos |
| author_facet | Patras, Alexandros Lalis, Spyros Antonopoulos, Christos D. Bellas, Nikolaos |
| contents | Heterogeneous embedded systems, with diverse computing elements and accelerators such as FPGAs, offer a promising platform for fast and flexible ML inference, which is crucial for services such as autonomous driving and augmented reality, where delays can be costly. However, efficiently allocating computational resources for deep learning applications in FPGA-based systems is a challenging task. A Deep Learning Processor Unit (DPU) is a parameterizable FPGA-based accelerator module optimized for ML inference. It supports a wide range of ML models and can be instantiated multiple times within a single FPGA to enable concurrent execution. This paper introduces DPUConfig, a novel runtime management framework, based on a custom Reinforcement Learning (RL) agent, that dynamically selects optimal DPU configurations by leveraging real-time telemetry data monitoring, system utilization, power consumption, and application performance to inform its configuration selection decisions. The experimental evaluation demonstrates that the RL agent achieves energy efficiency 95% (on average) of the optimal attainable energy efficiency for several CNN models on the Xilinx Zynq UltraScale+ MPSoC ZCU102. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_12847 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | DPUConfig: Optimizing ML Inference in FPGAs Using Reinforcement Learning Patras, Alexandros Lalis, Spyros Antonopoulos, Christos D. Bellas, Nikolaos Hardware Architecture Heterogeneous embedded systems, with diverse computing elements and accelerators such as FPGAs, offer a promising platform for fast and flexible ML inference, which is crucial for services such as autonomous driving and augmented reality, where delays can be costly. However, efficiently allocating computational resources for deep learning applications in FPGA-based systems is a challenging task. A Deep Learning Processor Unit (DPU) is a parameterizable FPGA-based accelerator module optimized for ML inference. It supports a wide range of ML models and can be instantiated multiple times within a single FPGA to enable concurrent execution. This paper introduces DPUConfig, a novel runtime management framework, based on a custom Reinforcement Learning (RL) agent, that dynamically selects optimal DPU configurations by leveraging real-time telemetry data monitoring, system utilization, power consumption, and application performance to inform its configuration selection decisions. The experimental evaluation demonstrates that the RL agent achieves energy efficiency 95% (on average) of the optimal attainable energy efficiency for several CNN models on the Xilinx Zynq UltraScale+ MPSoC ZCU102. |
| title | DPUConfig: Optimizing ML Inference in FPGAs Using Reinforcement Learning |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2602.12847 |