Implementation and Performance Evaluation of CMOS-integrated Memristor-driven Flip-flop Circuits
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arXiv
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| Autores principales: | , , , , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866911448530157568 |
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| author | Tiwari, Paras Dhakad, Narendra Singh Rani, Shalu Kumar, Sanjay Prodromakis, Themis |
| author_facet | Tiwari, Paras Dhakad, Narendra Singh Rani, Shalu Kumar, Sanjay Prodromakis, Themis |
| contents | In this work, we report implementation and performance evaluation of memristor-driven fundamental logic gates, including NOT, AND, NAND, OR, NOR, and XOR, and novel and optimized design of the sequential logic circuits, such as D flip-flop, T-flip-flop, JK-flip-flop, and SR-flip-flop. The design, implementation, and optimization of these logic circuits were performed in SPECTRE in Cadence Virtuoso and integrated with 90 nm CMOS technology node. Additionally, we discuss an optimized design of memristor-driven logic gates and sequential logic circuits, and draw a comparative analysis with the other reported state-of-the-art work on sequential circuits. Moreover, the utilized memristor framework was experimentally pre-validated with the experimental data of Y2O3-based memristive devices, which shows significantly low values of variability during switching in both device-to-device (D2D) and cycle-to-cycle (C2C) operation. The performance metrics were calculated in terms of area, power, and delay of these sequential circuits and were found to be reduced by more than ~24%, 60%, and 58%, respectively, as compared to the other state-of-the-art work on sequential circuits. Therefore, the implemented memristor-based design significantly improves the performance of various logic designs, which makes it more area and power-efficient and shows the potential of memristor in designing various low-power, low-cost, ultrafast, and compact circuits. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_13825 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Implementation and Performance Evaluation of CMOS-integrated Memristor-driven Flip-flop Circuits Tiwari, Paras Dhakad, Narendra Singh Rani, Shalu Kumar, Sanjay Prodromakis, Themis Hardware Architecture Applied Physics In this work, we report implementation and performance evaluation of memristor-driven fundamental logic gates, including NOT, AND, NAND, OR, NOR, and XOR, and novel and optimized design of the sequential logic circuits, such as D flip-flop, T-flip-flop, JK-flip-flop, and SR-flip-flop. The design, implementation, and optimization of these logic circuits were performed in SPECTRE in Cadence Virtuoso and integrated with 90 nm CMOS technology node. Additionally, we discuss an optimized design of memristor-driven logic gates and sequential logic circuits, and draw a comparative analysis with the other reported state-of-the-art work on sequential circuits. Moreover, the utilized memristor framework was experimentally pre-validated with the experimental data of Y2O3-based memristive devices, which shows significantly low values of variability during switching in both device-to-device (D2D) and cycle-to-cycle (C2C) operation. The performance metrics were calculated in terms of area, power, and delay of these sequential circuits and were found to be reduced by more than ~24%, 60%, and 58%, respectively, as compared to the other state-of-the-art work on sequential circuits. Therefore, the implemented memristor-based design significantly improves the performance of various logic designs, which makes it more area and power-efficient and shows the potential of memristor in designing various low-power, low-cost, ultrafast, and compact circuits. |
| title | Implementation and Performance Evaluation of CMOS-integrated Memristor-driven Flip-flop Circuits |
| topic | Hardware Architecture Applied Physics |
| url | https://arxiv.org/abs/2602.13825 |