Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866910025523396608 |
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| author | Kanda, R. Blevec, H. L. Onizawa, N. Leonardon, M. Gripon, V. Hanyu, T. |
| author_facet | Kanda, R. Blevec, H. L. Onizawa, N. Leonardon, M. Gripon, V. Hanyu, T. |
| contents | In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-based conventional design environments limited hardware implementations to fixed-point bit-widths of 16 or 32 bits. To address this, we adopt the FINN framework, enabling implementations with arbitrary bit-widths. Several customizations and minor adjustments are made, including: 1.Optimization of Transpose nodes to resolve data format mismatches, 2.Addition of handling for converting the final reduce mean operation to Global Average Pooling (GAP). These adjustments allow us to reduce the bit-width while maintaining the same accuracy as the conventional realization, and achieve approximately twice the throughput in evaluations using CIFAR-10 dataset. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2602_16024 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware Kanda, R. Blevec, H. L. Onizawa, N. Leonardon, M. Gripon, V. Hanyu, T. Hardware Architecture In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-based conventional design environments limited hardware implementations to fixed-point bit-widths of 16 or 32 bits. To address this, we adopt the FINN framework, enabling implementations with arbitrary bit-widths. Several customizations and minor adjustments are made, including: 1.Optimization of Transpose nodes to resolve data format mismatches, 2.Addition of handling for converting the final reduce mean operation to Global Average Pooling (GAP). These adjustments allow us to reduce the bit-width while maintaining the same accuracy as the conventional realization, and achieve approximately twice the throughput in evaluations using CIFAR-10 dataset. |
| title | Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2602.16024 |