Cover Image

DARTH-PUM: A Hybrid Processing-Using-Memory Architecture

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Wong, Ryan, Feinberg, Ben, Ghose, Saugata
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Cryptography and Security Emerging Technologies Machine Learning
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
by: Ovy, Sanwar Ahmed, et al.
Published: (2025)

TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates
by: Sahruri, Abdullah, et al.
Published: (2025)

ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption
by: Yune, Sungwoong, et al.
Published: (2025)

Do Not Trust Power Management: A Survey on Internal Energy-based Attacks Circumventing Trusted Execution Environments Security Properties
by: Gonidec, Gwenn Le, et al.
Published: (2024)

Research Directions for Verifiable Crypto-Physically Secure TEEs
by: Bellemare, Sylvain
Published: (2024)

Control-Flow Attestation: Concepts, Solutions, and Open Challenges
by: Sha, Zhanyu, et al.
Published: (2024)

Memristor-Based Lightweight Encryption
by: Siddiqi, Muhammad Ali, et al.
Published: (2024)

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
by: Razmkhah, Sasan, et al.
Published: (2025)

CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures
by: Pelke, Rebecca, et al.
Published: (2024)

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
by: Ferro, Elena, et al.
Published: (2024)

HePGA: A Heterogeneous Processing-in-Memory based GNN Training Accelerator
by: Ogbogu, Chukwufumnanya, et al.
Published: (2025)

OPIMA: Optical Processing-In-Memory for Convolutional Neural Network Acceleration
by: Sunny, Febin, et al.
Published: (2024)

Modeling and Simulation Frameworks for Processing-in-Memory Architectures
by: Aghaei, Mahdi, et al.
Published: (2025)

RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration
by: Zhao, Lei, et al.
Published: (2023)

CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems
by: Amin, Md Hasibul, et al.
Published: (2025)

Associative Memory Based Experience Replay for Deep Reinforcement Learning
by: Li, Mengyuan, et al.
Published: (2022)

RETENTION: Resource-Efficient Tree-Based Ensemble Model Acceleration with Content-Addressable Memory
by: Liao, Yi-Chun, et al.
Published: (2025)

Bulk-Switching Memristor-based Compute-In-Memory Module for Deep Neural Network Training
by: Wu, Yuting, et al.
Published: (2023)

Walking Noise: On Layer-Specific Robustness of Neural Architectures against Noisy Computations and Associated Characteristic Learning Dynamics
by: Borras, Hendrik, et al.
Published: (2022)

In-Memory Learning Automata Architecture using Y-Flash Cell
by: Ghazal, Omar, et al.
Published: (2024)

Towards Efficient Hyperdimensional Computing Using Photonics
by: Fayza, Farbin, et al.
Published: (2023)

H3PIMAP: A Heterogeneity-Aware Multi-Objective DNN Mapping Framework on Electronic-Photonic Processing-in-Memory Architectures
by: Yin, Ziang, et al.
Published: (2025)

Architectural and System Implications of CXL-enabled Tiered Memory
by: Yang, Yujie, et al.
Published: (2025)

IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference
by: Ghazal, Omar, et al.
Published: (2024)

Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM
by: Hajisadeghi, Amir M., et al.
Published: (2024)

A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions
by: M, Amogh K, et al.
Published: (2025)

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms
by: Silvano, Cristina, et al.
Published: (2023)

Running Conventional Automatic Speech Recognition on Memristor Hardware: A Simulated Approach
by: Rossenbach, Nick, et al.
Published: (2025)

Integrated Security Mechanisms for Weight Protection in Memristive Crossbar Arrays
by: Rahman, Muhammad Faheemur, et al.
Published: (2025)

MPAI: A Co-Processing Architecture with MPSoC & AI Accelerators for Vision Applications in Space
by: Leon, Vasileios, et al.
Published: (2024)

SCATTER: Algorithm-Circuit Co-Sparse Photonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light Redistribution
by: Yin, Ziang, et al.
Published: (2024)

Learning-driven Physically-aware Large-scale Circuit Gate Sizing
by: Ye, Yuyang, et al.
Published: (2024)

Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving
by: Pan, Yue, et al.
Published: (2025)

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
by: Tsaras, Dimitris, et al.
Published: (2025)

Hardware-Efficient Photonic Tensor Core: Accelerating Deep Neural Networks with Structured Compression
by: Ning, Shupeng, et al.
Published: (2025)

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks
by: Ahmed, Soyed Tuhin, et al.
Published: (2024)

Full-Stack Optimization for CAM-Only DNN Inference
by: de Lima, João Paulo C., et al.
Published: (2024)

Fast offset corrected in-memory training
by: Rasch, Malte J., et al.
Published: (2023)

Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations
by: Ahmed, Soyed Tuhin, et al.
Published: (2024)

Toward Digital Twins in 3D IC Packaging: A Critical Review of Physics, Data, and Hybrid Architectures
by: Datta, Gourab, et al.
Published: (2026)