Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA

Fuente: arXiv
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Hauptverfasser: Jeziorek, Kamil, Wzorek, Piotr, Blachut, Krzysztof, Nakano, Hiroshi, Dampfhoffer, Manon, Mesquida, Thomas, Nishi, Hiroaki, Dalgaty, Thomas, Kryjak, Tomasz
Format: Preprint
Veröffentlicht: 2026
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author Jeziorek, Kamil
Wzorek, Piotr
Blachut, Krzysztof
Nakano, Hiroshi
Dampfhoffer, Manon
Mesquida, Thomas
Nishi, Hiroaki
Dalgaty, Thomas
Kryjak, Tomasz
author_facet Jeziorek, Kamil
Wzorek, Piotr
Blachut, Krzysztof
Nakano, Hiroshi
Dampfhoffer, Manon
Mesquida, Thomas
Nishi, Hiroaki
Dalgaty, Thomas
Kryjak, Tomasz
contents As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a growing need for hardware-aware neural architectures that enable efficient, low-latency, and energy-conscious local processing. We present an FPGA implementation of event-graph neural networks for audio processing. We utilise an artificial cochlea that converts time-series signals into sparse event data, reducing memory and computation costs. Our architecture was implemented on a SoC FPGA and evaluated on two open-source datasets. For classification task, our baseline floating-point model achieves 92.7% accuracy on SHD dataset - only 2.4% below the state of the art - while requiring over 10x and 67x fewer parameters. On SSC, our models achieve 66.9-71.0% accuracy. Compared to FPGA-based spiking neural networks, our quantised model reaches 92.3% accuracy, outperforming them by up to 19.3% while reducing resource usage and latency. For SSC, we report the first hardware-accelerated evaluation. We further demonstrate the first end-to-end FPGA implementation of event-audio keyword spotting, combining graph convolutional layers with recurrent sequence modelling. The system achieves up to 95% word-end detection accuracy, with only 10.53 microsecond latency and 1.18 W power consumption, establishing a strong benchmark for energy-efficient event-driven KWS.
format Preprint
id arxiv_https___arxiv_org_abs_2602_16442
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA
Jeziorek, Kamil
Wzorek, Piotr
Blachut, Krzysztof
Nakano, Hiroshi
Dampfhoffer, Manon
Mesquida, Thomas
Nishi, Hiroaki
Dalgaty, Thomas
Kryjak, Tomasz
Machine Learning
Artificial Intelligence
Sound
Audio and Speech Processing
As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a growing need for hardware-aware neural architectures that enable efficient, low-latency, and energy-conscious local processing. We present an FPGA implementation of event-graph neural networks for audio processing. We utilise an artificial cochlea that converts time-series signals into sparse event data, reducing memory and computation costs. Our architecture was implemented on a SoC FPGA and evaluated on two open-source datasets. For classification task, our baseline floating-point model achieves 92.7% accuracy on SHD dataset - only 2.4% below the state of the art - while requiring over 10x and 67x fewer parameters. On SSC, our models achieve 66.9-71.0% accuracy. Compared to FPGA-based spiking neural networks, our quantised model reaches 92.3% accuracy, outperforming them by up to 19.3% while reducing resource usage and latency. For SSC, we report the first hardware-accelerated evaluation. We further demonstrate the first end-to-end FPGA implementation of event-audio keyword spotting, combining graph convolutional layers with recurrent sequence modelling. The system achieves up to 95% word-end detection accuracy, with only 10.53 microsecond latency and 1.18 W power consumption, establishing a strong benchmark for energy-efficient event-driven KWS.
title Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA
topic Machine Learning
Artificial Intelligence
Sound
Audio and Speech Processing
url https://arxiv.org/abs/2602.16442