Cita APA (7a ed.)

Wang, X., Raikar, R., Rein, M., Chen, R., Meng, C., & Stroobandt, D. (2026). Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs.

Cita Chicago Style (17a ed.)

Wang, Xiaoke, Raveena Raikar, Markus Rein, Ruiqi Chen, Chang Meng, y Dirk Stroobandt. Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs. 2026.

Cita MLA (9a ed.)

Wang, Xiaoke, et al. Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs. 2026.