APA (7th ed.) Citation

Wang, X., Raikar, R., Rein, M., Chen, R., Meng, C., & Stroobandt, D. (2026). Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs.

Chicago Style (17th ed.) Citation

Wang, Xiaoke, Raveena Raikar, Markus Rein, Ruiqi Chen, Chang Meng, and Dirk Stroobandt. Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs. 2026.

MLA (9th ed.) Citation

Wang, Xiaoke, et al. Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs. 2026.