:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Wang, Xiaoke, Raikar, Raveena, Rein, Markus, Chen, Ruiqi, Meng, Chang, Stroobandt, Dirk
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2602.19720
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy
by: Wang, Xiaoke, et al.
Published: (2025)

QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs
by: Shi, Jian, et al.
Published: (2024)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
by: Böttcher, Andreas, et al.
Published: (2024)

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
by: Böttcher, Andreas, et al.
Published: (2024)

Link Quality Aware Pathfinding for Chiplet Interconnects
by: Yen, Aaron, et al.
Published: (2026)

Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
by: Jiang, He, et al.
Published: (2025)

Resource Utilization of Differentiable Logic Gate Networks Deployed on FPGAs
by: Wormald, Stephen, et al.
Published: (2026)

PD-Swap: Prefill-Decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration
by: Zhang, Yifan, et al.
Published: (2025)

RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
by: Tan, Hongshi, et al.
Published: (2026)

Wavelet Based Frequency Detection Using FPGAs
by: Hill, Caleb, et al.
Published: (2024)

Data-Rate-Aware High-Speed CNN Inference on FPGAs
by: Habermann, Tobias, et al.
Published: (2026)

A Hybrid Delay Model for Interconnected Multi-Input Gates
by: Ferdowsi, Arman, et al.
Published: (2024)

Duet: Creating Harmony between Processors and Embedded FPGAs
by: Li, Ang, et al.
Published: (2023)

Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
by: Lanzieri, Leandro, et al.
Published: (2024)

Design and Implementation of Washing Machine HUD Using FPGAs
by: Stites, Norman, et al.
Published: (2025)

DPUConfig: Optimizing ML Inference in FPGAs Using Reinforcement Learning
by: Patras, Alexandros, et al.
Published: (2026)

Fast Generation of Custom Floating-Point Spatial Filters on FPGAs
by: Campos, Nelson, et al.
Published: (2024)

smallNet: Implementation of a convolutional layer in tiny FPGAs
by: Bascuñán, Fernanda Zapata, et al.
Published: (2025)

GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
by: Sudarshan, Chetan Choppali, et al.
Published: (2023)

Lightweight Congruence Profiling for Early Design Exploration of Heterogeneous FPGAs
by: Boston, Allen, et al.
Published: (2025)

Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs
by: Govindasamy, Hariprasadh, et al.
Published: (2024)

Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs
by: Taka, Endri, et al.
Published: (2024)

RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
by: Fu, Zizhuo, et al.
Published: (2026)

Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
by: Hao, Cong, et al.
Published: (2026)

LlamaF: An Efficient Llama2 Architecture Accelerator on Embedded FPGAs
by: Xu, Han, et al.
Published: (2024)

ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
by: Manca, Federico, et al.
Published: (2024)

A Survey on LUT-based Deep Neural Networks Implemented in FPGAs
by: Guo, Zeyu
Published: (2025)

Coyote v2: Raising the Level of Abstraction for Data Center FPGAs
by: Ramhorst, Benjamin, et al.
Published: (2025)

GraphMatch: Subgraph Query Processing on FPGAs
by: Dann, Jonas, et al.
Published: (2024)

Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs
by: Han, Zhaoyang, et al.
Published: (2025)

Energy Efficient LSTM Accelerators for Embedded FPGAs through Parameterised Architecture Design
by: Qian, Chao, et al.
Published: (2026)

A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
by: Magalhães, Philippe, et al.
Published: (2025)

Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs
by: Kida, Misaki, et al.
Published: (2025)

Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
by: Souvatzoglou, Ioanna, et al.
Published: (2024)

An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
by: Castelino, Cornell, et al.
Published: (2024)

Post-Quantum and Blockchain-Based Attestation for Trusted FPGAs in B5G Networks
by: Papalamprou, Ilias, et al.
Published: (2025)

A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
by: Galimberti, Andrea, et al.
Published: (2025)

Preemption-Enhanced Benchmark Suite for FPGAs
by: Malik, Arsalan Ali, et al.
Published: (2025)

Testing and Fault Tolerance Techniques for CNT-Based FPGAs
by: Lu, Siyuan, et al.
Published: (2025)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
by: Wang, Zhao, et al.
Published: (2021)