Image de couverture de livre

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Wang, Xiaoke, Raikar, Raveena, Rein, Markus, Chen, Ruiqi, Meng, Chang, Stroobandt, Dirk
Format:	Preprint
Publié:	2026
Sujets:	Hardware Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy
par: Wang, Xiaoke, et autres
Publié: (2025)

QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs
par: Shi, Jian, et autres
Publié: (2024)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
par: Böttcher, Andreas, et autres
Publié: (2024)

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
par: Böttcher, Andreas, et autres
Publié: (2024)

Link Quality Aware Pathfinding for Chiplet Interconnects
par: Yen, Aaron, et autres
Publié: (2026)

Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
par: Jiang, He, et autres
Publié: (2025)

PD-Swap: Prefill-Decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration
par: Zhang, Yifan, et autres
Publié: (2025)

Resource Utilization of Differentiable Logic Gate Networks Deployed on FPGAs
par: Wormald, Stephen, et autres
Publié: (2026)

RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
par: Tan, Hongshi, et autres
Publié: (2026)

Wavelet Based Frequency Detection Using FPGAs
par: Hill, Caleb, et autres
Publié: (2024)

A Hybrid Delay Model for Interconnected Multi-Input Gates
par: Ferdowsi, Arman, et autres
Publié: (2024)

Duet: Creating Harmony between Processors and Embedded FPGAs
par: Li, Ang, et autres
Publié: (2023)

Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
par: Lanzieri, Leandro, et autres
Publié: (2024)

Design and Implementation of Washing Machine HUD Using FPGAs
par: Stites, Norman, et autres
Publié: (2025)

Data-Rate-Aware High-Speed CNN Inference on FPGAs
par: Habermann, Tobias, et autres
Publié: (2026)

DPUConfig: Optimizing ML Inference in FPGAs Using Reinforcement Learning
par: Patras, Alexandros, et autres
Publié: (2026)

Fast Generation of Custom Floating-Point Spatial Filters on FPGAs
par: Campos, Nelson, et autres
Publié: (2024)

smallNet: Implementation of a convolutional layer in tiny FPGAs
par: Bascuñán, Fernanda Zapata, et autres
Publié: (2025)

GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
par: Sudarshan, Chetan Choppali, et autres
Publié: (2023)

Lightweight Congruence Profiling for Early Design Exploration of Heterogeneous FPGAs
par: Boston, Allen, et autres
Publié: (2025)

Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs
par: Govindasamy, Hariprasadh, et autres
Publié: (2024)

Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs
par: Taka, Endri, et autres
Publié: (2024)

RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
par: Fu, Zizhuo, et autres
Publié: (2026)

Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
par: Hao, Cong, et autres
Publié: (2026)

LlamaF: An Efficient Llama2 Architecture Accelerator on Embedded FPGAs
par: Xu, Han, et autres
Publié: (2024)

ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
par: Manca, Federico, et autres
Publié: (2024)

A Survey on LUT-based Deep Neural Networks Implemented in FPGAs
par: Guo, Zeyu
Publié: (2025)

Coyote v2: Raising the Level of Abstraction for Data Center FPGAs
par: Ramhorst, Benjamin, et autres
Publié: (2025)

Energy Efficient LSTM Accelerators for Embedded FPGAs through Parameterised Architecture Design
par: Qian, Chao, et autres
Publié: (2026)

A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
par: Magalhães, Philippe, et autres
Publié: (2025)

Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs
par: Kida, Misaki, et autres
Publié: (2025)

Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
par: Souvatzoglou, Ioanna, et autres
Publié: (2024)

An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
par: Castelino, Cornell, et autres
Publié: (2024)

GraphMatch: Subgraph Query Processing on FPGAs
par: Dann, Jonas, et autres
Publié: (2024)

Post-Quantum and Blockchain-Based Attestation for Trusted FPGAs in B5G Networks
par: Papalamprou, Ilias, et autres
Publié: (2025)

A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
par: Galimberti, Andrea, et autres
Publié: (2025)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
par: Wang, Zhao, et autres
Publié: (2021)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
par: Iff, Patrick, et autres
Publié: (2025)

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
par: Harlikar, Pracheta, et autres
Publié: (2025)

PipeOrgan: Efficient Inter-operation Pipelining with Flexible Spatial Organization and Interconnects
par: Garg, Raveesh, et autres
Publié: (2024)