FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption
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| Main Authors: | , , , , , , , , , , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866908853007810560 |
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| author | Daksha, Lohit Guzelhan, Seyda Shivdikar, Kaustubh Domingo, Carlos Agulló Lopez, Óscar Vera Jonatan, Gilbert Dymarkowski, Hubert Jerari, Aymane El Cano, José Abellán, José L. Kim, John Kaeli, David Joshi, Ajay |
| author_facet | Daksha, Lohit Guzelhan, Seyda Shivdikar, Kaustubh Domingo, Carlos Agulló Lopez, Óscar Vera Jonatan, Gilbert Dymarkowski, Hubert Jerari, Aymane El Cano, José Abellán, José L. Kim, John Kaeli, David Joshi, Ajay |
| contents | Fully Homomorphic Encryption (FHE) enables computation directly on encrypted data but incurs massive computational and memory overheads, often exceeding plaintext execution by several orders of magnitude. While custom ASIC accelerators can mitigate these costs, their long time-to-market and the rapid evolution of FHE algorithms threaten their long-term relevance. GPUs, by contrast, offer scalability, programmability, and widespread availability, making them an attractive platform for FHE. However, modern GPUs are increasingly specialized for machine learning workloads, emphasizing low-precision datatypes (e.g., INT$8$, FP$8$) that are fundamentally mismatched to the wide-precision modulo arithmetic required by FHE. Essentially, while GPUs offer ample parallelism, their functional units, like Tensor Cores, are not suited for wide-integer modulo arithmetic required by FHE schemes such as CKKS. Despite this constraint, researchers have attempted to map FHE primitives on Tensor Cores by segmenting wide integers into low-precision (INT$8$) chunks.
To overcome these bottlenecks, we propose FHECore, a specialized functional unit integrated directly into the GPU's Streaming Multiprocessor. Our design is motivated by a key insight: the two dominant contributors to latency$-$Number Theoretic Transform and Base Conversion$-$can be formulated as modulo-linear transformations. This allows them to be mapped on a common hardware unit that natively supports wide-precision modulo-multiply-accumulate operations. Our simulations demonstrate that FHECore reduces dynamic instruction count by a geometric mean of $2.41\times$ for CKKS primitives and $1.96\times$ for end-to-end workloads. These reductions translate to performance speedups of $1.57\times$ and $2.12\times$, respectively$-$including a $50\%$ reduction in bootstrapping latency$-$all while inuring a modest $2.4\%$ area overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2602_22229 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption Daksha, Lohit Guzelhan, Seyda Shivdikar, Kaustubh Domingo, Carlos Agulló Lopez, Óscar Vera Jonatan, Gilbert Dymarkowski, Hubert Jerari, Aymane El Cano, José Abellán, José L. Kim, John Kaeli, David Joshi, Ajay Hardware Architecture Cryptography and Security Fully Homomorphic Encryption (FHE) enables computation directly on encrypted data but incurs massive computational and memory overheads, often exceeding plaintext execution by several orders of magnitude. While custom ASIC accelerators can mitigate these costs, their long time-to-market and the rapid evolution of FHE algorithms threaten their long-term relevance. GPUs, by contrast, offer scalability, programmability, and widespread availability, making them an attractive platform for FHE. However, modern GPUs are increasingly specialized for machine learning workloads, emphasizing low-precision datatypes (e.g., INT$8$, FP$8$) that are fundamentally mismatched to the wide-precision modulo arithmetic required by FHE. Essentially, while GPUs offer ample parallelism, their functional units, like Tensor Cores, are not suited for wide-integer modulo arithmetic required by FHE schemes such as CKKS. Despite this constraint, researchers have attempted to map FHE primitives on Tensor Cores by segmenting wide integers into low-precision (INT$8$) chunks. To overcome these bottlenecks, we propose FHECore, a specialized functional unit integrated directly into the GPU's Streaming Multiprocessor. Our design is motivated by a key insight: the two dominant contributors to latency$-$Number Theoretic Transform and Base Conversion$-$can be formulated as modulo-linear transformations. This allows them to be mapped on a common hardware unit that natively supports wide-precision modulo-multiply-accumulate operations. Our simulations demonstrate that FHECore reduces dynamic instruction count by a geometric mean of $2.41\times$ for CKKS primitives and $1.96\times$ for end-to-end workloads. These reductions translate to performance speedups of $1.57\times$ and $2.12\times$, respectively$-$including a $50\%$ reduction in bootstrapping latency$-$all while inuring a modest $2.4\%$ area overhead. |
| title | FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption |
| topic | Hardware Architecture Cryptography and Security |
| url | https://arxiv.org/abs/2602.22229 |