Citazione Stile APA (7a Edizione)

Choi, J., Pant, K. A., Nam, Y., Hellmann, H., Nune, K., & Hwang, I. (2026). Signal Temporal Logic Verification and Synthesis Using Deep Reachability Analysis and Layered Control Architecture.

Citazione stile Chigago Style (17a edizione)

Choi, Joonwon, Kartik Anand Pant, Youngim Nam, Henry Hellmann, Karthik Nune, e Inseok Hwang. Signal Temporal Logic Verification and Synthesis Using Deep Reachability Analysis and Layered Control Architecture. 2026.

Citatione MLA (9a ed.)

Choi, Joonwon, et al. Signal Temporal Logic Verification and Synthesis Using Deep Reachability Analysis and Layered Control Architecture. 2026.