Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Liu, Yuhao, Ullah, Salim, Kumar, Akash
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Internet

https://arxiv.org/abs/2602.23334