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Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators

Fuente: arXiv

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Bibliographic Details
Main Authors:	Liu, Yuhao, Ullah, Salim, Kumar, Akash
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
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