Capstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers
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arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2026
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| _version_ | 1866908858724646912 |
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| author | Yarzada, Sabrina Torng, Christopher |
| author_facet | Yarzada, Sabrina Torng, Christopher |
| contents | Coarse-grained reconfigurable arrays (CGRAs) have attracted growing interest because they exhibit performance and energy efficiency competitive with ASICs while maintaining flexibility similar to FPGAs. These properties make CGRAs attractive in accelerator and other power-constrained system contexts. However, modern CGRA compilers aggressively pipeline for frequency and performance improvements, often violating hard power budgets. We empirically show that, in state-of-the-art CGRA compilers such as Cascade, post-place-and-route (post-PnR) pipelining increases power monotonically and ultimately exceeds fixed power caps across diverse workloads. In response, we introduce \emph{Capstone}, a power-aware extension of Cascade that integrates a fast, compiler-resident power model with a user-tunable controller that guides the bitstream selection process towards optimization targets. Capstone predicts per-iteration power directly inside the post-PnR compilation loop and selects one or a small set of PnR configurations such that at least one meets a user-specified power cap. Thus, we shift the objective from indiscriminately maximizing frequency to maximizing safe frequency under a discrete power cap. On a suite of kernels spanning fundamental dense and sparse applications, Capstone meets a power cap and minimizes remaining power headroom while preserving feasible performance. Our results indicate that cap-aware compilation is both necessary and practical, as the compiler can proactively land on cap-compliant points and expose predictable performance under power constraints. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_00909 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Capstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers Yarzada, Sabrina Torng, Christopher Hardware Architecture Coarse-grained reconfigurable arrays (CGRAs) have attracted growing interest because they exhibit performance and energy efficiency competitive with ASICs while maintaining flexibility similar to FPGAs. These properties make CGRAs attractive in accelerator and other power-constrained system contexts. However, modern CGRA compilers aggressively pipeline for frequency and performance improvements, often violating hard power budgets. We empirically show that, in state-of-the-art CGRA compilers such as Cascade, post-place-and-route (post-PnR) pipelining increases power monotonically and ultimately exceeds fixed power caps across diverse workloads. In response, we introduce \emph{Capstone}, a power-aware extension of Cascade that integrates a fast, compiler-resident power model with a user-tunable controller that guides the bitstream selection process towards optimization targets. Capstone predicts per-iteration power directly inside the post-PnR compilation loop and selects one or a small set of PnR configurations such that at least one meets a user-specified power cap. Thus, we shift the objective from indiscriminately maximizing frequency to maximizing safe frequency under a discrete power cap. On a suite of kernels spanning fundamental dense and sparse applications, Capstone meets a power cap and minimizes remaining power headroom while preserving feasible performance. Our results indicate that cap-aware compilation is both necessary and practical, as the compiler can proactively land on cap-compliant points and expose predictable performance under power constraints. |
| title | Capstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.00909 |