Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow
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arXiv
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| Format: | Preprint |
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2026
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| author | Gu, Hang Wang, Teng Cheng, Qianyu Li, Jinao Zheng, Zhendong Gong, Lei Lou, Wenqi Li, Xi Zhou, Xuehai |
| author_facet | Gu, Hang Wang, Teng Cheng, Qianyu Li, Jinao Zheng, Zhendong Gong, Lei Lou, Wenqi Li, Xi Zhou, Xuehai |
| contents | Fully Homomorphic Encryption (FHE) relies heavily on the Number Theoretic Transform (NTT), making NTT a major performance bottleneck due to its intensive polynomial computations. Hybrid Homomorphic Encryption (HHE), which integrates arithmetic and logic FHE, further requires support for multiple NTT lengths. However, existing accelerators mainly optimize NTT throughput and do not provide unified support for HHE. This paper presents Hermes, a unified high-performance NTT architecture based on hybrid dataflow. Hermes exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core. A conflict-free on-chip fragmentation algorithm is introduced to resolve bank conflicts and enable burst HBM access, while an efficient dataflow improves computational intensity through data reuse, reducing bandwidth demand. Experimental results show that Hermes supports multiple NTT lengths and achieves up to 13.6x and 1.3x higher throughput than state-of-the-art GPU and FPGA accelerators, respectively. Our source code is available at https://anonymous.4open.science/r/Hermes_conf-4E6F. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_01556 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow Gu, Hang Wang, Teng Cheng, Qianyu Li, Jinao Zheng, Zhendong Gong, Lei Lou, Wenqi Li, Xi Zhou, Xuehai Hardware Architecture Fully Homomorphic Encryption (FHE) relies heavily on the Number Theoretic Transform (NTT), making NTT a major performance bottleneck due to its intensive polynomial computations. Hybrid Homomorphic Encryption (HHE), which integrates arithmetic and logic FHE, further requires support for multiple NTT lengths. However, existing accelerators mainly optimize NTT throughput and do not provide unified support for HHE. This paper presents Hermes, a unified high-performance NTT architecture based on hybrid dataflow. Hermes exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core. A conflict-free on-chip fragmentation algorithm is introduced to resolve bank conflicts and enable burst HBM access, while an efficient dataflow improves computational intensity through data reuse, reducing bandwidth demand. Experimental results show that Hermes supports multiple NTT lengths and achieves up to 13.6x and 1.3x higher throughput than state-of-the-art GPU and FPGA accelerators, respectively. Our source code is available at https://anonymous.4open.science/r/Hermes_conf-4E6F. |
| title | Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.01556 |