Copertina

TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link

Fuente: arXiv

Salvato in:

Dettagli Bibliografici
Autori principali:	Zhang, Yichao, Bertuletti, Marco, Zhang, Chi, Riedel, Samuel, Shen, Diyou, Wang, Bowen, Vanelli-Coralli, Alessandro, Benini, Luca
Natura:	Preprint
Pubblicazione:	2026
Soggetti:	Distributed, Parallel, and Cluster Computing Hardware Architecture
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

Documenti analoghi

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios
di: Zhang, Yichao, et al.
Pubblicazione: (2024)

TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks
di: Bertuletti, Marco, et al.
Pubblicazione: (2026)

A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR
di: Zhang, Yichao, et al.
Pubblicazione: (2024)

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
di: Mazzola, Sergio, et al.
Pubblicazione: (2025)

TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs
di: Shen, Diyou, et al.
Pubblicazione: (2025)

A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment
di: Wang, Bowen, et al.
Pubblicazione: (2025)

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
di: Riedel, Samuel, et al.
Pubblicazione: (2025)

A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks
di: Bertuletti, Marco, et al.
Pubblicazione: (2025)

Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters
di: Mazzola, Sergio, et al.
Pubblicazione: (2024)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
di: Perotti, Matteo, et al.
Pubblicazione: (2023)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
di: Tedeschi, Riccardo, et al.
Pubblicazione: (2025)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
di: Cammarata, Danilo, et al.
Pubblicazione: (2025)

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
di: Perotti, Matteo, et al.
Pubblicazione: (2024)

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
di: Benz, Thomas, et al.
Pubblicazione: (2025)

A Compute&Memory Efficient Model-Driven Neural 5G Receiver for Edge AI-assisted RAN
di: Abdollahpour, Mahdi, et al.
Pubblicazione: (2025)

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN
di: Zhang, Yichao, et al.
Pubblicazione: (2025)

Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks
di: Bertuletti, Marco, et al.
Pubblicazione: (2025)

Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores
di: Colagrande, Luca, et al.
Pubblicazione: (2026)

TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters
di: Zhang, Yichao, et al.
Pubblicazione: (2025)

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
di: Koenig, Cyril, et al.
Pubblicazione: (2025)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
di: Perotti, Matteo, et al.
Pubblicazione: (2024)

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
di: Colagrande, Luca, et al.
Pubblicazione: (2025)

Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGA
di: Li, Jindong, et al.
Pubblicazione: (2025)

TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads
di: Purayil, Navaneeth Kunhi, et al.
Pubblicazione: (2025)

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
di: Reinwardt, Christopher, et al.
Pubblicazione: (2025)

CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
di: Goswami, Kaustav, et al.
Pubblicazione: (2026)

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
di: Purayil, Navaneeth Kunhi, et al.
Pubblicazione: (2025)

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
di: Rogenmoser, Michael, et al.
Pubblicazione: (2023)

Toleo: Scaling Freshness to Tera-scale Memory using CXL and PIM
di: Dong, Juechu, et al.
Pubblicazione: (2024)

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
di: Colagrande, Luca, et al.
Pubblicazione: (2025)

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
di: Scheffler, Paul, et al.
Pubblicazione: (2024)

Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting
di: Kadiyala, Divya Kiran, et al.
Pubblicazione: (2025)

Reimagining Memory Access for LLM Inference: Compression-Aware Memory Controller Design
di: Xie, Rui, et al.
Pubblicazione: (2025)

Exploring DRAM Cache Prefetching for Pooled Memory
di: Tirumalasetty, Chandrahas, et al.
Pubblicazione: (2024)

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm
di: Rogenmoser, Michael, et al.
Pubblicazione: (2023)

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
di: Manoni, Simone, et al.
Pubblicazione: (2025)

Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
di: Li, Yinrong, et al.
Pubblicazione: (2026)

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
di: Perotti, Matteo, et al.
Pubblicazione: (2022)

Ecco: Improving Memory Bandwidth and Capacity for LLMs via Entropy-aware Cache Compression
di: Cheng, Feng, et al.
Pubblicazione: (2025)

Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory
di: Hong, Jeongmin, et al.
Pubblicazione: (2024)