Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866913040276914176 |
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| author | Tang, Jiaping Mu, Jianan Ma, Tianyun Chao, Zhiteng Ye, Jing Li, Huawei |
| author_facet | Tang, Jiaping Mu, Jianan Ma, Tianyun Chao, Zhiteng Ye, Jing Li, Huawei |
| contents | Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bug localization techniques have achieved remarkable success in software domains and shown promise for hardware description languages, their effectiveness severely degrades in sequential designs. Unlike software programs, hardware designs exhibit intrinsic temporal characteristics that create fundamental challenges: timing misalignment between bug activation and observation, and progressive error propagation through state elements that obscures the root cause. To address these limitations, we propose Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs. Our approach introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles to identify potential activation cycles, strategic trace pruning to eliminate state pollution effects. We evaluate Pecker on comprehensive benchmarks comprising both combinational and sequential circuits. Experimental results demonstrate that Pecker effectively localizes 51%/80%/85% bugs within Top-1/3/5 ranks respectively, significantly outperforming state-of-the-art techniques. Notably, Pecker maintains robust performance across circuit complexities while existing methods exhibit severe degradation on sequential designs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_02583 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction Tang, Jiaping Mu, Jianan Ma, Tianyun Chao, Zhiteng Ye, Jing Li, Huawei Hardware Architecture Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bug localization techniques have achieved remarkable success in software domains and shown promise for hardware description languages, their effectiveness severely degrades in sequential designs. Unlike software programs, hardware designs exhibit intrinsic temporal characteristics that create fundamental challenges: timing misalignment between bug activation and observation, and progressive error propagation through state elements that obscures the root cause. To address these limitations, we propose Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs. Our approach introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles to identify potential activation cycles, strategic trace pruning to eliminate state pollution effects. We evaluate Pecker on comprehensive benchmarks comprising both combinational and sequential circuits. Experimental results demonstrate that Pecker effectively localizes 51%/80%/85% bugs within Top-1/3/5 ranks respectively, significantly outperforming state-of-the-art techniques. Notably, Pecker maintains robust performance across circuit complexities while existing methods exhibit severe degradation on sequential designs. |
| title | Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.02583 |