Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference
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arXiv
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| Autori principali: | , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866917309016178688 |
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| author | Liu, Yiqi Pan, Yudong Wang, Mengdi Zhao, Shixin Zhu, Haonan Han, Yinhe Zhang, Lei Wang, Ying |
| author_facet | Liu, Yiqi Pan, Yudong Wang, Mengdi Zhao, Shixin Zhu, Haonan Han, Yinhe Zhang, Lei Wang, Ying |
| contents | Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based Computing-in-Memory (CIM) architecture that executes all operations in situ, eliminating off-chip migration. To maximize its limited first-level capacity, we introduce three innovations:
Token-Grained Pipelining: Replaces sequence-level pipelining to mitigate length variations, boosting utilization and reducing activation storage. Distributed Dynamic KV Cache Management: Decouples memory from compute to leverage fragmented SRAM for efficient KV storage. Communication-Aware Mapping: Optimizes core allocation for locality and fault tolerance across the wafer.
Experimental results show Ouroboros achieves average gains of $4.1\times$ in throughput and $4.2\times$ in energy efficiency, peaking at $9.1\times$ and $17\times$ for the 13B model.
(*Due to the notification of arXiv "The Abstract field cannot be longer than 1,920 characters", the appeared Abstract is shortened. For the full Abstract, please download the Article.) |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_02737 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference Liu, Yiqi Pan, Yudong Wang, Mengdi Zhao, Shixin Zhu, Haonan Han, Yinhe Zhang, Lei Wang, Ying Hardware Architecture Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based Computing-in-Memory (CIM) architecture that executes all operations in situ, eliminating off-chip migration. To maximize its limited first-level capacity, we introduce three innovations: Token-Grained Pipelining: Replaces sequence-level pipelining to mitigate length variations, boosting utilization and reducing activation storage. Distributed Dynamic KV Cache Management: Decouples memory from compute to leverage fragmented SRAM for efficient KV storage. Communication-Aware Mapping: Optimizes core allocation for locality and fault tolerance across the wafer. Experimental results show Ouroboros achieves average gains of $4.1\times$ in throughput and $4.2\times$ in energy efficiency, peaking at $9.1\times$ and $17\times$ for the 13B model. (*Due to the notification of arXiv "The Abstract field cannot be longer than 1,920 characters", the appeared Abstract is shortened. For the full Abstract, please download the Article.) |
| title | Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.02737 |