TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866911482553303040 |
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| author | Koutayni, Mhd Rashed Al Selim, Mohamed Reis, Gerd Pagani, Alain Stricker, Didier |
| author_facet | Koutayni, Mhd Rashed Al Selim, Mohamed Reis, Gerd Pagani, Alain Stricker, Didier |
| contents | Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_03075 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference Koutayni, Mhd Rashed Al Selim, Mohamed Reis, Gerd Pagani, Alain Stricker, Didier Computer Vision and Pattern Recognition Artificial Intelligence Hardware Architecture Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems. |
| title | TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference |
| topic | Computer Vision and Pattern Recognition Artificial Intelligence Hardware Architecture |
| url | https://arxiv.org/abs/2603.03075 |