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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2026
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| Accès en ligne: | https://arxiv.org/abs/2603.03598 |
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| _version_ | 1866911483733999616 |
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| author | Wickramasinghe, Sachini Ye, Tian Raghavendra, Cauligi Prasanna, Viktor |
| author_facet | Wickramasinghe, Sachini Ye, Tian Raghavendra, Cauligi Prasanna, Viktor |
| contents | Convolutional Neural Networks (CNNs) have achieved state-of-the-art accuracy in Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR). However, their high computational cost, latency, and memory footprint make its deployment challenging on resource-constrained platforms such as small satellites. While adversarial robustness is critical for real-world SAR ATR, it is often overlooked in system-level optimizations. Achieving both robustness and inference efficiency requires a unified framework that considers adversarially trained models together with hardware constraints. We present a model-hardware co-design framework for CNN-based SAR ATR that integrates robustness-preserving model compression with FPGA accelerator design. The compression stage includes hardware-guided structured pruning, where a hardware performance model derived from the FPGA design predicts the pruning impact on latency and resource usage. This enables the generation of Pareto-optimal models that improve hardware efficiency under user-defined objectives, while maintaining adversarial robustness within a predefined tolerance. We design an FPGA accelerator with channel-aware Processing Element (PE) allocation that supports both fully pipelined streaming and temporal resource-reuse architectures. An automated design generation flow efficiently maps the compressed models to optimized FPGA implementations. Experiments on the widely used MSTAR and FUSAR-Ship datasets across three CNN architectures show that our framework produces models up to 18.3x smaller with 3.1x fewer MACs while preserving robustness. Our FPGA implementation achieves up to 68.1x (6.4x) lower inference latency and up to 169.7x (33.2x) better energy efficiency compared to CPU (GPU) baselines, demonstrating the effectiveness of the proposed co-design framework for robust and efficient SAR ATR on FPGA platforms. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_03598 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | ARMOR: Robust and Efficient CNN-Based SAR ATR through Model-Hardware Co-Design Wickramasinghe, Sachini Ye, Tian Raghavendra, Cauligi Prasanna, Viktor Hardware Architecture Convolutional Neural Networks (CNNs) have achieved state-of-the-art accuracy in Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR). However, their high computational cost, latency, and memory footprint make its deployment challenging on resource-constrained platforms such as small satellites. While adversarial robustness is critical for real-world SAR ATR, it is often overlooked in system-level optimizations. Achieving both robustness and inference efficiency requires a unified framework that considers adversarially trained models together with hardware constraints. We present a model-hardware co-design framework for CNN-based SAR ATR that integrates robustness-preserving model compression with FPGA accelerator design. The compression stage includes hardware-guided structured pruning, where a hardware performance model derived from the FPGA design predicts the pruning impact on latency and resource usage. This enables the generation of Pareto-optimal models that improve hardware efficiency under user-defined objectives, while maintaining adversarial robustness within a predefined tolerance. We design an FPGA accelerator with channel-aware Processing Element (PE) allocation that supports both fully pipelined streaming and temporal resource-reuse architectures. An automated design generation flow efficiently maps the compressed models to optimized FPGA implementations. Experiments on the widely used MSTAR and FUSAR-Ship datasets across three CNN architectures show that our framework produces models up to 18.3x smaller with 3.1x fewer MACs while preserving robustness. Our FPGA implementation achieves up to 68.1x (6.4x) lower inference latency and up to 169.7x (33.2x) better energy efficiency compared to CPU (GPU) baselines, demonstrating the effectiveness of the proposed co-design framework for robust and efficient SAR ATR on FPGA platforms. |
| title | ARMOR: Robust and Efficient CNN-Based SAR ATR through Model-Hardware Co-Design |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.03598 |