Dissipation-Reliability Tradeoff for Stochastic CMOS Bits in Series
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arXiv
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| Auteurs principaux: | , , , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866917315260448768 |
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| author | Murphy, Cathryn Nicholson, Schuyler Freitas, Nahuel Penocchio, Emanuele Gingrich, Todd |
| author_facet | Murphy, Cathryn Nicholson, Schuyler Freitas, Nahuel Penocchio, Emanuele Gingrich, Todd |
| contents | Physical instantiations of a bit of information are subject to thermal noise that can trigger unintended bit-flip errors. Bits implemented with CMOS technology typically operate in regimes that reliably suppress these errors with a large bias voltage, but miniaturization and circuit design for implantable biomedical devices motivate error suppression via alternative low-voltage strategies. We present and analyze an error-suppression technique that involves coupling multiple CMOS units into chains, introducing a natural error correction arising from inter-unit correlations. Using tensor networks to numerically solve a stochastic master equation for the CMOS chain, we quantify the reliability-dissipation tradeoff across system sizes that would be intractable with conventional sparse-matrix methods. The calculations show that the typical time for bit-flip errors scales exponentially with the bias voltage but subexponentially with the chain length. While a CMOS chain adds stability compared to a single CMOS unit for a fixed low bias voltage, increasing the bias voltage is a lower-dissipation route to equivalent stability. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_04658 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Dissipation-Reliability Tradeoff for Stochastic CMOS Bits in Series Murphy, Cathryn Nicholson, Schuyler Freitas, Nahuel Penocchio, Emanuele Gingrich, Todd Statistical Mechanics Physical instantiations of a bit of information are subject to thermal noise that can trigger unintended bit-flip errors. Bits implemented with CMOS technology typically operate in regimes that reliably suppress these errors with a large bias voltage, but miniaturization and circuit design for implantable biomedical devices motivate error suppression via alternative low-voltage strategies. We present and analyze an error-suppression technique that involves coupling multiple CMOS units into chains, introducing a natural error correction arising from inter-unit correlations. Using tensor networks to numerically solve a stochastic master equation for the CMOS chain, we quantify the reliability-dissipation tradeoff across system sizes that would be intractable with conventional sparse-matrix methods. The calculations show that the typical time for bit-flip errors scales exponentially with the bias voltage but subexponentially with the chain length. While a CMOS chain adds stability compared to a single CMOS unit for a fixed low bias voltage, increasing the bias voltage is a lower-dissipation route to equivalent stability. |
| title | Dissipation-Reliability Tradeoff for Stochastic CMOS Bits in Series |
| topic | Statistical Mechanics |
| url | https://arxiv.org/abs/2603.04658 |