CktEvo: Repository-Level RTL Code Benchmark for Design Evolution

Fuente: arXiv
Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Shi, Zhengyuan, Wang, Jingxin, Cheng, Tairan, Xu, Changran, Qian, Weikang, Xu, Qiang
Format: Preprint
Veröffentlicht: 2026
Schlagworte:
Online-Zugang:
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
_version_ 1866910046998233088
author Shi, Zhengyuan
Wang, Jingxin
Cheng, Tairan
Xu, Changran
Qian, Weikang
Xu, Qiang
author_facet Shi, Zhengyuan
Wang, Jingxin
Cheng, Tairan
Xu, Changran
Qian, Weikang
Xu, Qiang
contents Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downstream toolchain. While large language models (LLMs) have recently been applied to hardware design, most efforts focus on generation or debugging from natural-language prompts, where ambiguity and hallucinations necessitate expert review. A separate line of work begins from formal inputs, yet typically optimizes high-level synthesis or isolated modules and remains decoupled from cross-file dependencies. In this work, we present CktEvo, a benchmark and reference framework for repo-level RTL evolution. Unlike prior benchmarks consisting of isolated snippets, our benchmark targets complete IP cores where PPA emerges from cross-file dependencies. Our benchmark packages several high-quality Verilog repositories from real-world designs. We formalize the task as: given an initial repository, produce edits that preserve functional behavior while improving PPA. We also provide a closed-loop framework that couples LLM-proposed edits with toolchain feedback to enable cross-file modifications and iterative repair at repository scale. Our experiments demonstrate that the reference framework realizes PPA improvements without any human interactions. CktEvo establishes a rigorous and executable foundation for studying LLM-assisted RTL optimization that matters for engineering practice: repository-level, function-preserving, and PPA-driven.
format Preprint
id arxiv_https___arxiv_org_abs_2603_08718
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
Shi, Zhengyuan
Wang, Jingxin
Cheng, Tairan
Xu, Changran
Qian, Weikang
Xu, Qiang
Hardware Architecture
Artificial Intelligence
Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downstream toolchain. While large language models (LLMs) have recently been applied to hardware design, most efforts focus on generation or debugging from natural-language prompts, where ambiguity and hallucinations necessitate expert review. A separate line of work begins from formal inputs, yet typically optimizes high-level synthesis or isolated modules and remains decoupled from cross-file dependencies. In this work, we present CktEvo, a benchmark and reference framework for repo-level RTL evolution. Unlike prior benchmarks consisting of isolated snippets, our benchmark targets complete IP cores where PPA emerges from cross-file dependencies. Our benchmark packages several high-quality Verilog repositories from real-world designs. We formalize the task as: given an initial repository, produce edits that preserve functional behavior while improving PPA. We also provide a closed-loop framework that couples LLM-proposed edits with toolchain feedback to enable cross-file modifications and iterative repair at repository scale. Our experiments demonstrate that the reference framework realizes PPA improvements without any human interactions. CktEvo establishes a rigorous and executable foundation for studying LLM-assisted RTL optimization that matters for engineering practice: repository-level, function-preserving, and PPA-driven.
title CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
topic Hardware Architecture
Artificial Intelligence
url https://arxiv.org/abs/2603.08718