AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding
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| Main Authors: | , , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866914541796851712 |
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| author | Kim, Seungmin Kim, Mingun Lee, Yuna Kim, Yulhwa |
| author_facet | Kim, Seungmin Kim, Mingun Lee, Yuna Kim, Yulhwa |
| contents | Analog circuit design remains highly dependent on expert knowledge due to the complexity of device-level interactions and topology design. Recent transformer-based approaches for device-level topology generation have shown promise, yet they suffer from low electrical validity without human-in-the-loop (HITL) training and severe memorization caused by sequence-based circuit representations. In this work, we propose AnalogToBi, a framework for device-level analog circuit topology generation. AnalogToBi introduces circuit-type conditioning for categorizing heterogeneous multi-type topology datasets, device renaming augmentation to mitigate memorization, a bipartite graph representation for improved structural generalization, and grammar-guided decoding to enforce structural validity during bipartite graph generation. Experimental results demonstrate that AnalogToBi achieves high validity and novelty without HITL training while effectively avoiding memorization of training topologies. Our code is available at https://github.com/Seungmin0825/AnalogToBi. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_08720 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding Kim, Seungmin Kim, Mingun Lee, Yuna Kim, Yulhwa Hardware Architecture Emerging Technologies Analog circuit design remains highly dependent on expert knowledge due to the complexity of device-level interactions and topology design. Recent transformer-based approaches for device-level topology generation have shown promise, yet they suffer from low electrical validity without human-in-the-loop (HITL) training and severe memorization caused by sequence-based circuit representations. In this work, we propose AnalogToBi, a framework for device-level analog circuit topology generation. AnalogToBi introduces circuit-type conditioning for categorizing heterogeneous multi-type topology datasets, device renaming augmentation to mitigate memorization, a bipartite graph representation for improved structural generalization, and grammar-guided decoding to enforce structural validity during bipartite graph generation. Experimental results demonstrate that AnalogToBi achieves high validity and novelty without HITL training while effectively avoiding memorization of training topologies. Our code is available at https://github.com/Seungmin0825/AnalogToBi. |
| title | AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2603.08720 |