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| Main Author: | |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2603.08732 |
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| _version_ | 1866911500495486976 |
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| author | Liguori, Vincenzo |
| author_facet | Liguori, Vincenzo |
| contents | This paper shows that, for matrix multiplications and convolutions, it is possible to asymptotically replace each real multiplication with a single squaring operation. Similarly, a single complex multiplication can be replaced with 3 squaring operations. Given that an n bits squaring circuit requires about half the gate count of an nxn multiplier, this results in large resource reductions. With some caveats, the same techniques can apply to dot products, transformations and more. A varietiy of architectures implementing these ideas in hardware are described, including square based systolic arrays and tensor cores. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_08732 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Fair and Square: Replacing One Real Multiplication with a Single Square and One Complex Multiplication with Three Squares When Performing Matrix Multiplication and Convolutions Liguori, Vincenzo Hardware Architecture This paper shows that, for matrix multiplications and convolutions, it is possible to asymptotically replace each real multiplication with a single squaring operation. Similarly, a single complex multiplication can be replaced with 3 squaring operations. Given that an n bits squaring circuit requires about half the gate count of an nxn multiplier, this results in large resource reductions. With some caveats, the same techniques can apply to dot products, transformations and more. A varietiy of architectures implementing these ideas in hardware are described, including square based systolic arrays and tensor cores. |
| title | Fair and Square: Replacing One Real Multiplication with a Single Square and One Complex Multiplication with Three Squares When Performing Matrix Multiplication and Convolutions |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.08732 |