Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs
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arXiv
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| Hauptverfasser: | , , |
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| Format: | Preprint |
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2026
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| _version_ | 1866913017945391104 |
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| author | Shashidhar, Vishal Kumari, Anupam Paily, Roy P |
| author_facet | Shashidhar, Vishal Kumari, Anupam Paily, Roy P |
| contents | Modern CNNs' high computational demands hinder edge deployment, as traditional ``hard'' sparsity (skipping mathematical zeros) loses effectiveness in deep layers or with smooth activations like Tanh. We propose a ``soft sparsity'' paradigm using a hardware efficient Most Significant Bit (MSB) proxy to skip negligible non-zero multiplications. Integrated as a custom RISC-V instruction and evaluated on LeNet-5 (MNIST), this method reduces ReLU MACs by 88.42% and Tanh MACs by 74.87% with zero accuracy loss--outperforming zero-skipping by 5x. By clock-gating inactive multipliers, we estimate power savings of 35.2% for ReLU and 29.96% for Tanh. While memory access makes power reduction sub-linear to operation savings, this approach significantly optimizes resource-constrained inference. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_10100 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs Shashidhar, Vishal Kumari, Anupam Paily, Roy P Machine Learning Artificial Intelligence Hardware Architecture Modern CNNs' high computational demands hinder edge deployment, as traditional ``hard'' sparsity (skipping mathematical zeros) loses effectiveness in deep layers or with smooth activations like Tanh. We propose a ``soft sparsity'' paradigm using a hardware efficient Most Significant Bit (MSB) proxy to skip negligible non-zero multiplications. Integrated as a custom RISC-V instruction and evaluated on LeNet-5 (MNIST), this method reduces ReLU MACs by 88.42% and Tanh MACs by 74.87% with zero accuracy loss--outperforming zero-skipping by 5x. By clock-gating inactive multipliers, we estimate power savings of 35.2% for ReLU and 29.96% for Tanh. While memory access makes power reduction sub-linear to operation savings, this approach significantly optimizes resource-constrained inference. |
| title | Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs |
| topic | Machine Learning Artificial Intelligence Hardware Architecture |
| url | https://arxiv.org/abs/2603.10100 |