In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs

Documenti analoghi

• Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
  di: Darvishi, Mostafa
  Pubblicazione: (2026)
• A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs
  di: Darvishi, Mostafa
  Pubblicazione: (2025)
• Practical Timing Closure in FPGA and ASIC Designs: Methods, Challenges, and Case Studies
  di: Darvishi, Mostafa
  Pubblicazione: (2025)
• Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
  di: Darvishi, Mostafa
  Pubblicazione: (2025)
• Single-Event Upset Analysis of a Systolic Array based Deep Neural Network Accelerator
  di: Jonckers, Naïn, et al.
  Pubblicazione: (2024)