VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866918508687785984 |
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| author | Hu, Runbang Fang, Bo Li, Bingzhe Ji, Yuede |
| author_facet | Hu, Runbang Fang, Bo Li, Bingzhe Ji, Yuede |
| contents | As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_11075 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification Hu, Runbang Fang, Bo Li, Bingzhe Ji, Yuede Hardware Architecture Artificial Intelligence As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics. |
| title | VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2603.11075 |