Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
Fuente:
arXiv
Guardado en:
| Autores principales: | Fu, Weimin, Wang, Zeng, Shao, Minghao, Karri, Ramesh, Shafique, Muhammad, Knechtel, Johann, Sinanoglu, Ozgur, Guo, Xiaolong |
|---|---|
| Formato: | Preprint |
| Publicado: |
2026
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
por: Shao, Minghao, et al.
Publicado: (2026)
por: Shao, Minghao, et al.
Publicado: (2026)
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
por: Fu, Weimin, et al.
Publicado: (2026)
por: Fu, Weimin, et al.
Publicado: (2026)
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
por: Sreekumar, Saideep, et al.
Publicado: (2026)
por: Sreekumar, Saideep, et al.
Publicado: (2026)
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
por: Knechtel, Johann, et al.
Publicado: (2026)
por: Knechtel, Johann, et al.
Publicado: (2026)
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
por: Mankali, Lakshmi Likhitha, et al.
Publicado: (2024)
por: Mankali, Lakshmi Likhitha, et al.
Publicado: (2024)
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
por: Wang, Zeng, et al.
Publicado: (2025)
por: Wang, Zeng, et al.
Publicado: (2025)
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
por: Roy, Prithwish Basu, et al.
Publicado: (2025)
por: Roy, Prithwish Basu, et al.
Publicado: (2025)
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
por: Wang, Zeng, et al.
Publicado: (2025)
por: Wang, Zeng, et al.
Publicado: (2025)
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
por: Wang, Zeng, et al.
Publicado: (2024)
por: Wang, Zeng, et al.
Publicado: (2024)
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
por: Roy, Prithwish Basu, et al.
Publicado: (2026)
por: Roy, Prithwish Basu, et al.
Publicado: (2026)
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
por: Bhandari, Jitendra, et al.
Publicado: (2024)
por: Bhandari, Jitendra, et al.
Publicado: (2024)
Targeted Wearout Attacks in Microprocessor Cores
por: Mashburn, Joshua, et al.
Publicado: (2025)
por: Mashburn, Joshua, et al.
Publicado: (2025)
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
por: Hemadri, Raghu Vamshi, et al.
Publicado: (2025)
por: Hemadri, Raghu Vamshi, et al.
Publicado: (2025)
Logic Encryption: This Time for Real
por: Karn, Rupesh Raj, et al.
Publicado: (2025)
por: Karn, Rupesh Raj, et al.
Publicado: (2025)
Large Language Models (LLMs) for Electronic Design Automation (EDA)
por: Xu, Kangwei, et al.
Publicado: (2025)
por: Xu, Kangwei, et al.
Publicado: (2025)
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
por: Collini, Luca, et al.
Publicado: (2024)
por: Collini, Luca, et al.
Publicado: (2024)
Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog
por: Hatta, Naoya, et al.
Publicado: (2024)
por: Hatta, Naoya, et al.
Publicado: (2024)
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
por: DeLorenzo, Matthew, et al.
Publicado: (2024)
por: DeLorenzo, Matthew, et al.
Publicado: (2024)
FormalRTL: Verified RTL Synthesis at Scale
por: Li, Kezhi, et al.
Publicado: (2026)
por: Li, Kezhi, et al.
Publicado: (2026)
SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
por: Chang, Fu-Chieh, et al.
Publicado: (2026)
por: Chang, Fu-Chieh, et al.
Publicado: (2026)
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
por: Wang, Fangzhou, et al.
Publicado: (2024)
por: Wang, Fangzhou, et al.
Publicado: (2024)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
por: Yin, Shuo, et al.
Publicado: (2026)
por: Yin, Shuo, et al.
Publicado: (2026)
UVLLM: An Automated Universal RTL Verification Framework using LLMs
por: Hu, Yuchen, et al.
Publicado: (2024)
por: Hu, Yuchen, et al.
Publicado: (2024)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
por: Deng, Chenhui, et al.
Publicado: (2026)
por: Deng, Chenhui, et al.
Publicado: (2026)
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
por: Zhou, Jie, et al.
Publicado: (2025)
por: Zhou, Jie, et al.
Publicado: (2025)
A Quality-Aware Voltage Overscaling Framework to Improve the Energy Efficiency and Lifetime of TPUs based on Statistical Error Modeling
por: Senobari, Alireza, et al.
Publicado: (2024)
por: Senobari, Alireza, et al.
Publicado: (2024)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
por: Allam, Ahmed, et al.
Publicado: (2024)
por: Allam, Ahmed, et al.
Publicado: (2024)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
por: Liu, Shang, et al.
Publicado: (2025)
por: Liu, Shang, et al.
Publicado: (2025)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
por: Krupp, Lukas, et al.
Publicado: (2026)
por: Krupp, Lukas, et al.
Publicado: (2026)
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
por: Collini, Luca, et al.
Publicado: (2024)
por: Collini, Luca, et al.
Publicado: (2024)
FastCaps: A Design Methodology for Accelerating Capsule Network on Field Programmable Gate Arrays
por: Rahoof, Abdul, et al.
Publicado: (2025)
por: Rahoof, Abdul, et al.
Publicado: (2025)
Using LLMs to Facilitate Formal Verification of RTL
por: Orenes-Vera, Marcelo, et al.
Publicado: (2023)
por: Orenes-Vera, Marcelo, et al.
Publicado: (2023)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
por: Deng, Chenhui, et al.
Publicado: (2025)
por: Deng, Chenhui, et al.
Publicado: (2025)
ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis
por: Purini, Suresh, et al.
Publicado: (2025)
por: Purini, Suresh, et al.
Publicado: (2025)
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
por: Bhandari, Jitendra, et al.
Publicado: (2024)
por: Bhandari, Jitendra, et al.
Publicado: (2024)
MEIC: Re-thinking RTL Debug Automation using LLMs
por: Xu, Ke, et al.
Publicado: (2024)
por: Xu, Ke, et al.
Publicado: (2024)
Extend IVerilog to Support Batch RTL Fault Simulation
por: Tang, Jiaping, et al.
Publicado: (2025)
por: Tang, Jiaping, et al.
Publicado: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
por: Chen, Lu, et al.
Publicado: (2025)
por: Chen, Lu, et al.
Publicado: (2025)
CapsBeam: Accelerating Capsule Network based Beamformer for Ultrasound Non-Steered Plane Wave Imaging on Field Programmable Gate Array
por: Rahoof, Abdul, et al.
Publicado: (2025)
por: Rahoof, Abdul, et al.
Publicado: (2025)
TrojanLoC: LLM-based Framework for RTL Trojan Localization
por: Xiao, Weihua, et al.
Publicado: (2025)
por: Xiao, Weihua, et al.
Publicado: (2025)
Ejemplares similares
-
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
por: Shao, Minghao, et al.
Publicado: (2026) -
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
por: Fu, Weimin, et al.
Publicado: (2026) -
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
por: Sreekumar, Saideep, et al.
Publicado: (2026) -
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
por: Knechtel, Johann, et al.
Publicado: (2026) -
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
por: Mankali, Lakshmi Likhitha, et al.
Publicado: (2024)