CellE: Automated Standard Cell Library Extension via Equality Saturation
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arXiv
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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | |
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| _version_ | 1866912984794660864 |
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| author | Ren, Yi Wang, Yukun Meng, Xiang Cheng, Guoyao Peng, Baokang Zhang, Lining Lin, Yibo Wang, Runsheng Sun, Guangyu |
| author_facet | Ren, Yi Wang, Yukun Meng, Xiang Cheng, Guoyao Peng, Baokang Zhang, Lining Lin, Yibo Wang, Runsheng Sun, Guangyu |
| contents | Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_12797 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | CellE: Automated Standard Cell Library Extension via Equality Saturation Ren, Yi Wang, Yukun Meng, Xiang Cheng, Guoyao Peng, Baokang Zhang, Lining Lin, Yibo Wang, Runsheng Sun, Guangyu Hardware Architecture Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities. |
| title | CellE: Automated Standard Cell Library Extension via Equality Saturation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2603.12797 |