An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration
Fuente:
arXiv
Guardado en:
| Autores principales: | Cheng, Chung-Kuan, Kahng, Andrew B., Lin, Bill, Wang, Yucheng, Yoon, Dooseok |
|---|---|
| Formato: | Preprint |
| Publicado: |
2026
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
ArtNet: Hierarchical Clustering-Based Artificial Netlist Generator for ML and DTCO Application
por: Kang, Andrew B. Kahng. Seokhyeong, et al.
Publicado: (2025)
por: Kang, Andrew B. Kahng. Seokhyeong, et al.
Publicado: (2025)
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations
por: Holtz, Chester, et al.
Publicado: (2024)
por: Holtz, Chester, et al.
Publicado: (2024)
ChipletPart: Cost-Aware Partitioning for 2.5D Systems
por: Graening, Alexander, et al.
Publicado: (2025)
por: Graening, Alexander, et al.
Publicado: (2025)
DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators
por: Kahng, Andrew B., et al.
Publicado: (2024)
por: Kahng, Andrew B., et al.
Publicado: (2024)
Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
por: Hao, Cong, et al.
Publicado: (2026)
por: Hao, Cong, et al.
Publicado: (2026)
CellE: Automated Standard Cell Library Extension via Equality Saturation
por: Ren, Yi, et al.
Publicado: (2026)
por: Ren, Yi, et al.
Publicado: (2026)
Large Language Model (LLM) for Standard Cell Layout Design Optimization
por: Ho, Chia-Tung, et al.
Publicado: (2024)
por: Ho, Chia-Tung, et al.
Publicado: (2024)
Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research
por: Jiang, Liwen, et al.
Publicado: (2026)
por: Jiang, Liwen, et al.
Publicado: (2026)
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design
por: Liu, Bingyang, et al.
Publicado: (2024)
por: Liu, Bingyang, et al.
Publicado: (2024)
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
por: Di, Zhixiong, et al.
Publicado: (2023)
por: Di, Zhixiong, et al.
Publicado: (2023)
Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs
por: Wang, Runxi, et al.
Publicado: (2025)
por: Wang, Runxi, et al.
Publicado: (2025)
ALIGN: A System for Automating Analog Layout
por: Dhar, Tonmoy, et al.
Publicado: (2020)
por: Dhar, Tonmoy, et al.
Publicado: (2020)
High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator
por: Lin, Kuan-Ting, et al.
Publicado: (2025)
por: Lin, Kuan-Ting, et al.
Publicado: (2025)
Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations
por: Esmaeilzadeh, Hadi, et al.
Publicado: (2023)
por: Esmaeilzadeh, Hadi, et al.
Publicado: (2023)
Towards Performance-Aware Allocation for Accelerated Machine Learning on GPU-SSD Systems
por: Gundawar, Ayush, et al.
Publicado: (2024)
por: Gundawar, Ayush, et al.
Publicado: (2024)
YAP+: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding
por: Chen, Zhichao, et al.
Publicado: (2025)
por: Chen, Zhichao, et al.
Publicado: (2025)
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
por: Ferry, Corentin, et al.
Publicado: (2024)
por: Ferry, Corentin, et al.
Publicado: (2024)
An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell Library
por: Kamath, Akshay Karkal, et al.
Publicado: (2024)
por: Kamath, Akshay Karkal, et al.
Publicado: (2024)
Polaris: Multi-Fidelity Design Space Exploration of Deep Learning Accelerators
por: Sakhuja, Chirag, et al.
Publicado: (2024)
por: Sakhuja, Chirag, et al.
Publicado: (2024)
Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators
por: Liu, Qunyou, et al.
Publicado: (2025)
por: Liu, Qunyou, et al.
Publicado: (2025)
CPU-Based Layout Design for Picker-to-Parts Pallet Warehouses
por: Looms, Timo, et al.
Publicado: (2025)
por: Looms, Timo, et al.
Publicado: (2025)
Kugelblitz: Executable, Cost-Aware Design-Space Exploration for Programmable Packet Pipelines
por: Ageev, Artem, et al.
Publicado: (2023)
por: Ageev, Artem, et al.
Publicado: (2023)
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
por: Li, Wenkai, et al.
Publicado: (2025)
por: Li, Wenkai, et al.
Publicado: (2025)
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support
por: Diao, Haikang, et al.
Publicado: (2025)
por: Diao, Haikang, et al.
Publicado: (2025)
HeLEx: A Heterogeneous Layout Explorer for Spatial Elastic Coarse-Grained Reconfigurable Arrays
por: Du, Alan Jia Bao, et al.
Publicado: (2025)
por: Du, Alan Jia Bao, et al.
Publicado: (2025)
Voyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators
por: Prabhu, Kartik, et al.
Publicado: (2025)
por: Prabhu, Kartik, et al.
Publicado: (2025)
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration
por: Ghosh, Arkapravo, et al.
Publicado: (2025)
por: Ghosh, Arkapravo, et al.
Publicado: (2025)
AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout
por: Qin, Xian Rong, et al.
Publicado: (2026)
por: Qin, Xian Rong, et al.
Publicado: (2026)
Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
por: Geens, Robin, et al.
Publicado: (2026)
por: Geens, Robin, et al.
Publicado: (2026)
A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids
por: Shin, Taeho, et al.
Publicado: (2022)
por: Shin, Taeho, et al.
Publicado: (2022)
Computing-In-Memory Aware Model Adaption For Edge Devices
por: Lin, Ming-Han, et al.
Publicado: (2025)
por: Lin, Ming-Han, et al.
Publicado: (2025)
An Optimal Alignment-Driven Iterative Closed-Loop Convergence Framework for High-Performance Ultra-Large Scale Layout Pattern Clustering
por: Liu, Shuo
Publicado: (2025)
por: Liu, Shuo
Publicado: (2025)
DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization
por: Ren, Yi, et al.
Publicado: (2025)
por: Ren, Yi, et al.
Publicado: (2025)
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
por: Duan, Cenlin, et al.
Publicado: (2025)
por: Duan, Cenlin, et al.
Publicado: (2025)
HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
por: Tsai, Pei-Huan, et al.
Publicado: (2026)
por: Tsai, Pei-Huan, et al.
Publicado: (2026)
No One-Size-Fits-All: A Workload-Driven Characterization of Bit-Parallel vs. Bit-Serial Data Layouts for Processing-using-Memory
por: Zhang, Jingyao, et al.
Publicado: (2025)
por: Zhang, Jingyao, et al.
Publicado: (2025)
Scaling Routers with In-Package Optics and High-Bandwidth Memories
por: Keslassy, Isaac, et al.
Publicado: (2026)
por: Keslassy, Isaac, et al.
Publicado: (2026)
Predictive Software Scheduling as an Early-Warning Hint Layer for Optical Engine Thermal Drift in Heterogeneous SoIC Packaging
por: Chung, Chi Fei
Publicado: (2026)
por: Chung, Chi Fei
Publicado: (2026)
AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
por: Xue, Chenhao, et al.
Publicado: (2026)
por: Xue, Chenhao, et al.
Publicado: (2026)
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits
por: Chen, Yu, et al.
Publicado: (2025)
por: Chen, Yu, et al.
Publicado: (2025)
Ejemplares similares
-
ArtNet: Hierarchical Clustering-Based Artificial Netlist Generator for ML and DTCO Application
por: Kang, Andrew B. Kahng. Seokhyeong, et al.
Publicado: (2025) -
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations
por: Holtz, Chester, et al.
Publicado: (2024) -
ChipletPart: Cost-Aware Partitioning for 2.5D Systems
por: Graening, Alexander, et al.
Publicado: (2025) -
DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators
por: Kahng, Andrew B., et al.
Publicado: (2024) -
Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
por: Hao, Cong, et al.
Publicado: (2026)