Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866915863223861248 |
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| author | Antunes, Pedro Hafiz, Muhammad Ihsan Al Ekelund, Jonah Dineva, Ekaterina Miloshevich, George Gonidakis, Panagiotis Podobas, Artur |
| author_facet | Antunes, Pedro Hafiz, Muhammad Ihsan Al Ekelund, Jonah Dineva, Ekaterina Miloshevich, George Gonidakis, Panagiotis Podobas, Artur |
| contents | Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16$\times$ higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4$\times$ speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_14091 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference Antunes, Pedro Hafiz, Muhammad Ihsan Al Ekelund, Jonah Dineva, Ekaterina Miloshevich, George Gonidakis, Panagiotis Podobas, Artur Hardware Architecture Machine Learning Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16$\times$ higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4$\times$ speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions. |
| title | Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2603.14091 |