Co-Design of Memory-Storage Systems for Workload Awareness with Interpretable Models
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866917352224849920 |
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| author | Sarkar, Jay Rayaprolu, Vamsi Pavan Bhalerao, Abhijeet |
| author_facet | Sarkar, Jay Rayaprolu, Vamsi Pavan Bhalerao, Abhijeet |
| contents | Solid-state storage architectures based on NAND or emerging memory devices (SSD), are fundamentally architected and optimized for both reliability and performance. Achieving these simultaneous goals requires co-design of memory components with firmware-architected Error Management (EM) algorithms for density- and performance-scaled memory technologies. We describe a Machine Learning (ML) for systems methodology and modeling for co-designing the EM subsystem together with the natural variance inherent to scaled silicon process of memory components underlying SSD technology. The modeling analyzes NAND memory components and EM algorithms interacting with comprehensive suite of synthetic (stress-focused and JEDEC) and emulation (YCSB and similar) workloads across Flash Translation abstraction layers, by leveraging a statistically interpretable and intuitively explainable ML algorithm. The generalizable co-design framework evaluates several thousand datacenter SSDs spanning multiple generations of memory and storage technology. Consequently, the modeling framework enables continuous, holistic, data-driven design towards generational architectural advancements. We additionally demonstrate that the framework enables Representation Learning of the EM-workload domain for enhancement of the architectural design-space across broad spectrum of workloads. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_15571 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Co-Design of Memory-Storage Systems for Workload Awareness with Interpretable Models Sarkar, Jay Rayaprolu, Vamsi Pavan Bhalerao, Abhijeet Hardware Architecture Machine Learning Systems and Control Applied Physics B.8; C.4 Solid-state storage architectures based on NAND or emerging memory devices (SSD), are fundamentally architected and optimized for both reliability and performance. Achieving these simultaneous goals requires co-design of memory components with firmware-architected Error Management (EM) algorithms for density- and performance-scaled memory technologies. We describe a Machine Learning (ML) for systems methodology and modeling for co-designing the EM subsystem together with the natural variance inherent to scaled silicon process of memory components underlying SSD technology. The modeling analyzes NAND memory components and EM algorithms interacting with comprehensive suite of synthetic (stress-focused and JEDEC) and emulation (YCSB and similar) workloads across Flash Translation abstraction layers, by leveraging a statistically interpretable and intuitively explainable ML algorithm. The generalizable co-design framework evaluates several thousand datacenter SSDs spanning multiple generations of memory and storage technology. Consequently, the modeling framework enables continuous, holistic, data-driven design towards generational architectural advancements. We additionally demonstrate that the framework enables Representation Learning of the EM-workload domain for enhancement of the architectural design-space across broad spectrum of workloads. |
| title | Co-Design of Memory-Storage Systems for Workload Awareness with Interpretable Models |
| topic | Hardware Architecture Machine Learning Systems and Control Applied Physics B.8; C.4 |
| url | https://arxiv.org/abs/2603.15571 |