ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM
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arXiv
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| Format: | Preprint |
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2026
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| author | Zuepke, Alexander Pradhan, Ashutosh Ottaviano, Daniele Bastoni, Andrea Caccamo, Marco |
| author_facet | Zuepke, Alexander Pradhan, Ashutosh Ottaviano, Daniele Bastoni, Andrea Caccamo, Marco |
| contents | The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_16490 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM Zuepke, Alexander Pradhan, Ashutosh Ottaviano, Daniele Bastoni, Andrea Caccamo, Marco Performance Hardware Architecture The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol. |
| title | ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM |
| topic | Performance Hardware Architecture |
| url | https://arxiv.org/abs/2603.16490 |