An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
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arXiv
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| Main Authors: | Sekonji, Mohammad Javad, Mahani, Ali, Mirsadeghi, Maryam, Taheri, Mahdi |
|---|---|
| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | |
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