High-yield integration design of fixed-frequency superconducting qubit systems using siZZle-CZ gates
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arXiv
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866915885661290496 |
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| author | Ogawa, Kazuhisa Tabuchi, Yutaka Negoro, Makoto |
| author_facet | Ogawa, Kazuhisa Tabuchi, Yutaka Negoro, Makoto |
| contents | Fixed-frequency transmon qubits, characterized by simple architectures and long coherence times, are promising platforms for large-scale quantum computing. However, the rapidly increasing frequency collisions, which directly reduce the fabrication yield, hinder scaling, especially in cross-resonance (CR) gate-based architectures, wherein the restricted drive frequency severely limits the available design space. We investigate the Stark-induced ZZ by level excursions (siZZle) gate, which relaxes this limitation by allowing arbitrary drive-frequency choices. Extensive numerical analyses across a broad parameter range -- including the far-detuned regime that has received negligible prior attention -- reveal wide operating windows that support controlled-Z (CZ) fidelities >99.6%. Leveraging these windows, we design lattice architectures containing >1000 qubits, showing that even under 0.25% fabrication-induced frequency dispersion, the zero-collision yields in square and heavy-hexagonal lattices reach 80% and 100%, respectively. Thus, the siZZle-CZ gate is a scalable and collision-robust alternative to the CR gate, offering a viable route toward high-yield fixed-frequency transmon quantum processors. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_21537 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | High-yield integration design of fixed-frequency superconducting qubit systems using siZZle-CZ gates Ogawa, Kazuhisa Tabuchi, Yutaka Negoro, Makoto Quantum Physics Fixed-frequency transmon qubits, characterized by simple architectures and long coherence times, are promising platforms for large-scale quantum computing. However, the rapidly increasing frequency collisions, which directly reduce the fabrication yield, hinder scaling, especially in cross-resonance (CR) gate-based architectures, wherein the restricted drive frequency severely limits the available design space. We investigate the Stark-induced ZZ by level excursions (siZZle) gate, which relaxes this limitation by allowing arbitrary drive-frequency choices. Extensive numerical analyses across a broad parameter range -- including the far-detuned regime that has received negligible prior attention -- reveal wide operating windows that support controlled-Z (CZ) fidelities >99.6%. Leveraging these windows, we design lattice architectures containing >1000 qubits, showing that even under 0.25% fabrication-induced frequency dispersion, the zero-collision yields in square and heavy-hexagonal lattices reach 80% and 100%, respectively. Thus, the siZZle-CZ gate is a scalable and collision-robust alternative to the CR gate, offering a viable route toward high-yield fixed-frequency transmon quantum processors. |
| title | High-yield integration design of fixed-frequency superconducting qubit systems using siZZle-CZ gates |
| topic | Quantum Physics |
| url | https://arxiv.org/abs/2603.21537 |