Cover Image

Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Armato, Antonino, Kehl, Christian, Fischer, Sebastian
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Software Engineering
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)

A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs
by: Kumar, Aman, et al.
Published: (2024)

An Integrated Failure and Threat Mode and Effect Analysis (FTMEA) Framework with Quantified Cross-Domain Correlation Factors for Automotive Semiconductors
by: Armato, Antonino, et al.
Published: (2026)

ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions
by: Vavelidou, Ioanna, et al.
Published: (2026)

EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)

LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)

Offloading Data Center Tax
by: Revankar, Akshay, et al.
Published: (2025)

MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)

A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)

A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2024)

Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2025)

Scalable Software Testing in Fast Virtual Platforms: Leveraging SystemC, QEMU and Containerization
by: Jünger, Lukas, et al.
Published: (2025)

FVRuleLearner: Operator-Level Reasoning Tree (OP-Tree)-Based Rules Learning for Formal Verification
by: Wan, Lily Jiaxin, et al.
Published: (2026)

SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution
by: Li, Yufeng, et al.
Published: (2024)

Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
by: Liu, Jiale, et al.
Published: (2026)

The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages
by: Schreiner, Johannes, et al.
Published: (2024)

FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
by: Gadde, Deepak Narayan, et al.
Published: (2024)

GreenMalloc: Allocator Optimisation for Industrial Workloads
by: Dakhama, Aidan, et al.
Published: (2025)

Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms
by: Bosbach, Nils, et al.
Published: (2025)

Selective Parallel Loading of Large-Scale Compressed Graphs with ParaGrapher
by: Esfahani, Mohsen Koohi, et al.
Published: (2024)

HW/SW Co-design of a PCM/PWM converter: a System Level Approach based in the SpecC Methodology
by: Petrini, Daniel G. P., et al.
Published: (2025)

UCAgent: An End-to-End Agent for Block-Level Functional Verification
by: Wang, Junyue, et al.
Published: (2026)

DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)

Is Agentic AI Ready for Real-World Hardware Engineering? A Deep Dive with Phoenix-bench
by: Zou, Qingyun, et al.
Published: (2026)

KernelCraft: Benchmarking for Agentic Close-to-Metal Kernel Generation on Emerging Hardware
by: Nie, Jiayi, et al.
Published: (2026)

I hope we don't do to trust what advertising has done to love
by: Alglave, Jade
Published: (2026)

AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
by: Nadimi, Bardia, et al.
Published: (2026)

IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
by: Chen, Luanrong, et al.
Published: (2026)

ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
by: Wang, Bowei, et al.
Published: (2025)

A High-level Synthesis Toolchain for the Julia Language
by: Short, Benedict, et al.
Published: (2025)

DUET: Agentic Design Understanding via Experimentation and Testing
by: Smith, Gus Henry, et al.
Published: (2025)

Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
by: Gai, Jiahao, et al.
Published: (2025)

Testing Resource Isolation for System-on-Chip Architectures
by: Ledent, Philippe, et al.
Published: (2024)

RTLSquad: Multi-Agent Based Interpretable RTL Design
by: Wang, Bowei, et al.
Published: (2025)

Using LLM such as ChatGPT for Designing and Implementing a RISC Processor: Execution,Challenges and Limitations
by: Hossain, Shadeeb, et al.
Published: (2024)