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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2603.23762 |
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| _version_ | 1866915925904588800 |
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| author | Yuhala, Peterson Mwaisela, Mpoki Felber, Pascal Schiavoni, Valerio |
| author_facet | Yuhala, Peterson Mwaisela, Mpoki Felber, Pascal Schiavoni, Valerio |
| contents | Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing technology, achieve this by integrating low-power DRAM processing units (DPUs) into memory DIMMs, enabling massive parallelism and improved memory bandwidth. However, paradoxically, these PIM architectures introduce mandatory coarse-grained data transfers between host DRAM and DPUs, which often become the new bottleneck. We present PIM-CACHE, a lightweight data staging layer that dynamically eliminates redundant data transfers to PIM DPUs by exploiting workload similarity, achieving content-aware copy (CAC). We evaluate PIM-CACHE on both synthetic workloads and real-world genome datasets, demonstrating its effectiveness in reducing PIM data transfer overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2603_23762 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | PIM-CACHE: High-Efficiency Content-Aware Copy for Processing-In-Memory Yuhala, Peterson Mwaisela, Mpoki Felber, Pascal Schiavoni, Valerio Emerging Technologies Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing technology, achieve this by integrating low-power DRAM processing units (DPUs) into memory DIMMs, enabling massive parallelism and improved memory bandwidth. However, paradoxically, these PIM architectures introduce mandatory coarse-grained data transfers between host DRAM and DPUs, which often become the new bottleneck. We present PIM-CACHE, a lightweight data staging layer that dynamically eliminates redundant data transfers to PIM DPUs by exploiting workload similarity, achieving content-aware copy (CAC). We evaluate PIM-CACHE on both synthetic workloads and real-world genome datasets, demonstrating its effectiveness in reducing PIM data transfer overhead. |
| title | PIM-CACHE: High-Efficiency Content-Aware Copy for Processing-In-Memory |
| topic | Emerging Technologies |
| url | https://arxiv.org/abs/2603.23762 |