Surrogates, Spikes, and Sparsity: Performance Analysis and Characterization of SNN Hyperparameters on Hardware
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arXiv
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| Main Authors: | Aliyev, Ilkin, Lopez, Jesus, Adegbija, Tosiron |
|---|---|
| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | |
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